AT87C5103-ICSIL datasheet(35/64 Pages) ATMEL

35 / 64 page

AT8xC5103

4134C–8051–09/04

Power-down Mode

To save maximum power, a power-down mode can be invoked by software (refer to

Table 20, PCON register).

In power-down mode, the oscillator is stopped and the instruction that invoked power-

down mode is the last instruction executed. The internal RAM and SFRs retain their

value until the power-down mode is terminated. VCC can be lowered to save further

power. Either a hardware reset or an external interrupt can cause an exit from power-

down. To properly terminate power-down mode, the reset or external interrupt should

not be executed before VCC is restored to its normal operating level and must be held

active long enough for the oscillator to restart and stabilize.

Only external interrupts INT0, INT1 are useful for exiting from power-down. For that,

interrupt must be enabled and configured as level or edge sensitive interrupt input.

Holding the pin low restarts the oscillator but bringing the pin high completes the exit as

detailed in Figure 20. When both interrupts are enabled, the oscillator restarts as soon

as one of the two inputs is held low and power-down exit will be completed when the first

input is released. In this case the higher priority interrupt service routine is executed.

Once the interrupt is serviced, the next instruction to be executed after RETI will be the

one following the instruction that put AT8xC5103 into power-down mode.

Figure 20. Power-Down Exit Waveform

Exiting from power-down by reset redefines all the SFRs, exiting from power-down by

external interrupt does no affect the SFRs.

Exiting from power-down by either reset or external interrupt does not affect the internal

RAM content.

Note:

If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence

is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and

idle mode is not entered.

Table 21 shows the state of ports during idle and power-down modes.

Note:

1. Port 0 can force a 0 level. A ‘one’ will leave port floating.

INT1

INT0

XTALA

Power-down Phase

Oscillator Restart Phase

Active Phase

XTALB

Table 21. State of Ports(1)

Mode

Program Memory

PORT1

PORT3

Idle

Internal

Port Data

Power-down

Internal

Port Data

AT87C5103-ICSIL Datasheet(PDF) 35 Page - ATMEL Corporation

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