AT87C5103-ICSIL datasheet(59/64 Pages) ATMEL

59 / 64 page

AT8xC5103

4134C–8051–09/04

AC Testing Input/Output

Waveforms

Figure 33. AC Testing Input/Output Waveforms

AC inputs during testing are driven at VCC - 0.5 for a logic “1” and 0.45V for a logic “0”.

Timing measurement are made at VIH min for a logic “1” and VIL max for a logic “0”.

Float Waveforms

Figure 34. Float Waveforms

For timing purposes as port pin is no longer floating when a 100 mV change from load

voltage occurs and begins to float when a 100 mV change from the loaded VOH/VOL level

occurs. IOL/IOH ≥ ± 20 mA.

Clock Waveforms

Valid in normal clock mode. In X2 Mode XTAL2 signal must be changed to XTAL2

divided by 2.

Figure 35. Clock Waveforms

This diagram indicates when signals are clocked internally. The time it takes the signals

to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is

dependent on variables such as temperature and pin loading. Propagation also varies

from output to output and component. Typically though (TA=25°C fully loaded) RD and

WR propagation delays are approximately 50 ns. The other signals are typically 85 ns.

Propagation delays are incorporated in the AC specifications.

0.45 V

VCC-0.5V

0.2VCC+0.9

0.2VCC-0.1

INPUT/OUTPUT

VOL+0.1 V

VOH-0.1 V

FLOAT

VLOAD

VLOAD+0.1V

VLOAD-0.1V

CLOCK

XTAL2

INTERNAL

STATE4

STATE5

STATE6

STATE1

STATE2

STATE3

STATE4

STATE5

SERIAL PORT SHIFT CLOCK

PORT OPERATION

TXD (MODE 0)

RXD SAMPLED

P1, P3, P4 PINS SAMPLED

P1, P3, P4 PINS

MOV DEST PORT (P1, P3, P4)

(INCLUDES INT0, INT1, TO, T1)

OLD DATA

NEW DATA

P1P2

AT87C5103-ICSIL Datasheet(PDF) 59 Page - ATMEL Corporation

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