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IMX7DCEC Datasheet(PDF) 33 Page - NXP Semiconductors |
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IMX7DCEC Datasheet(HTML) 33 Page - NXP Semiconductors |
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33 / 161 page ![]() Electrical characteristics i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023 NXP Semiconductors 33 4.1.7.2 4.1.7.2 Power-Down modes Table 17 shows the USB interface current consumption with only the OTG block powered down. In Power-Down mode, everything is powered down, including the USB_VBUS valid comparators and their associated bandgap circuity in typical condition. Table 18 shows the USB interface current consumption in Power-Down mode. 4.1.8 PCIe phy 2.1 DC electrical characteristics Note: VDD should have no more than 40 mVpp AC power supply noise superimposed on the high power supply voltage for the PHY core (1.8 V nominal DC value). At the same time, VDD should have no more than 20 mVpp AC power supply noise superimposed on the low power supply voltage for the PHY core. The power supply voltage variation for the PHY core should have less than +/-5% including the board-level power supply variation and on-chip power supply variation due to the finite impedances in the package. Table 17. USB PHY current consumption with VBUS Valid Comparators disabled1 1 VBUS Valid comparators can be disabled through software by setting USBNC_OTG*_PHY_CFG2[OTGDISABLE0] to 1. This signal powers down only the VBUS Valid comparator, and does not control power to the Session Valid Comparator, ADP Probe and Sense comparators, or the ID detection circuitry. VDD_USB_OTG1_3P3_IN VDD_USB_OTG2_3P3_IN Current 730 uA 730 uA Table 18. USB PHY current consumption in Power-Down mode1 1 The VBUS Valid Comparators and their associated bandgap circuits can be disabled through software by setting USBNC_OTG*_PHY_CFG2[OTGDISABLE0] to 1 and USBNC_OTG*_PHY_CFG2[DRVVBUS0] to 0, respectively. VDD_USB_OTG1_3P3_IN VDD_USB_OTG2_3P3_IN Current 200 uA 200 uA Table 19. PCIe recommended operating conditions Parameter Description Min Max Unit VDD Low Power Supply Voltage for PHY Core 1 V 0.95 1.05 V High Power Supply Voltage for PHY Core 1.8 V 1.71 1.89 TA Commercial Temperature Range 0 70 °C TJ Simulation Junction Temperature Range -40 125 °C |
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