IMX7DCEC datasheet(99/161 Pages) NXP

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Electrical characteristics

i.MX 7Dual Family of Applications Processors Datasheet, Rev. 7, 09/2023

NXP Semiconductors

The following subsections describe the CSI timing in gated and ungated clock modes.

4.10.8 MIPI PHY timing parameters

4.10.8.1 This section describes MIPI PHY electrical specifications.Electrical and Timing

Information

Table 76. Electrical and Timing Information

Symbol

Parameters

Test Conditions

Min

Typ

Max

Unit

Input DC Specifications - Apply to DSI_CLK_P/DSI_CLK_N and DSI_DATA_P/DSI_DATA_N inputs

Input signal voltage range

Transient voltage range is

limited from -300 mV to

1600 mV

-50

—

1350

VLEAK

Input leakage current

VGNDSH(min) = VI =

VGNDSH(max) +

VOH(absmax)

Lane module in LP Receive

Mode

-10

—

VGNDSH

Ground Shift

—

-50

—

VOH(absmax)

Maximum transient output

voltage level

—

1.45

tvoh(absmax)

Maximum transient time

above VOH(absmax)

—

HS Line Drivers DC Specifications

|VOD|

HS Transmit Differential

output voltage magnitude

80 = RL< = 125 

140

200

270



|VOD|

Change in Differential output

voltage magnitude between

logic states

80 = RL< = 125 

—

VCMTX

Steady-state common-mode

output voltage.

80 = RL< = 125 

150

200

250



VCMTX(1,0)

Changes in steady-state

common-mode output voltage

between logic states

80 = RL< = 125 

—

VOHHS

HS output high voltage

80 = RL< = 125 

—

360

ZOS

Single-ended output

impedance.

—

62.5





ZOS

Single-ended output

impedance mismatch.

—

LP Line Drivers DC Specifications

VOL

Output low-level SE voltage

—

-50

VOH

Output high-level SE voltage

—

1.1

1.2

1.3

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