VT6306 datasheet(45/59 Pages) VIA

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VT6306 PCI 1394a Host Controller

Revision 1.16 July 19, 2002

-39-

Functional Descriptions

PHY Circuit Description

Pinless PLL and Clock Generation

The VT6306 PHY requires an external 24.576 MHz crystal as a reference. An external clock can also be provided instead of a

crystal. An internal oscillator drives an internal phase-locked loop (PLL), which generates the required 393.216 MHz reference

clock. This reference signal is internally divided to provide the clock signals used to control transmission of the outbound encoded

Strobe and Data information. A 49.152 MHz clock signal is used for resynchronization of the received data. The PLL requires no

external filter components, referred to as “pinless PLL”, saving board implementation cost.

Power Down and Auto Power Save

The power down function stops operation of the PLL and disables all circuits except the connection detection circuits and bias

detection circuits at the XTPBIAS pins. Port transmitter and receiver circuitry are also disabled automatically when the port is

disabled, suspended, or disconnected.

Pinless PHY RESET

The RESET# can be left unconnected for saving board implementation cost. The internal power good circuit generates the

required PHY reset if the RESET# pin is unconnected. The required reset time is at least 0.5 ms. The reset time can be extended if

an external RC network is implemented. The port transmitter and receiver circuitry is disabled during power down, during reset

(when the RESET# input pin is asserted low), when no active cable is connected to the port, or when controlled by the internal

arbitration logic.

Data Transmission

Data bits to be transmitted through the cable ports are latched internally in synchronization with the 49.152 MHz system clock.

These bits are combined serially, encoded, and transmitted at 98.304/196.608/392.216 Mbps (referred to as S100, S200, and

S400 speed, respectively) as the outbound data-strobe information stream. During transmission, the encoded data information is

transmitted differentially on the TPB cable pair(s), and the encoded strobe information is transmitted differentially on the TPA

cable pair(s).

Data Reception

During packet reception the TPA and TPB transmitters of the receiving cable port are disabled, and the receivers for that port are

enabled. The encoded data information is received on the TPA cable pair, and the encoded strobe information is received on the

TPB cable pair. The received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The

serial data bits are collected into two-bit, four-bit or eight-bit parallel streams (depending upon the indicated receive speed),

resynchronized to the local 49.152 MHz system clock and sent to the LLC. The retiming buffer can tolerate clock variation up to

+/-100 ppm (compared to peer PHY) with 4K bytes at 393.216 Mbps, 2K bytes at 196.608 Mbps, and 1K bets at 98.304 Mbps.

The received data is also transmitted (repeated) to the other active (connected) cable ports.

TPBIAS

Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and

arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel

monitors the incoming cable common-mode voltage to determine the speed of the next packet transmission (speed signaling) during

arbitration. In addition, the TPB channel monitors the incoming cable common-mode voltage on the TPB pair for the presence of

the peer PHY bias voltage. The VT6306 provides three independent 1.84V nominal bias voltages at the XTPBIAS pins. The bias

voltage, when seen through a cable by a remote receiver, indicates the presence of an active connection. The bias voltage source

must be stabilized by an external filter capacitor of 0.33 µF.

Bias-Detector / Connect-Detector / Bias-Discharger

The VT6306 supports suspend / resume / disable functions as defined in the IEEE P1394a V4.0 specification. The suspend

mechanism allows pairs of directly connected ports to be placed into a low power state while maintaining a port-to-port connection

between 1394 bus segments. While in a low power state, a port is unable to transmit or receive data transaction packets. However,

VT6306 Datasheet(PDF) 45 Page - VIA Technologies, Inc.

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