ADC3683 datasheet(30/70 Pages) TI1

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Normalized Frequency (Fs)

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

-120

-100

-80

-60

-40

-20

Decb

Passband

Transition Band

Alias Band

Attn Spec

Figure 7-29. Decimation by 16 Complex Frequency

Response

Normalized Frequency (Fs)

0.003

0.006

0.009

0.012

0.015

0.018

0.021

0.024

0.027

0.03

-0.2

-0.19

-0.18

-0.17

-0.16

-0.15

-0.14

-0.13

-0.12

-0.11

-0.1

Decb

Passband

Transition Band

Alias Band

Attn Spec

Figure 7-30. Decimation by 16 Complex Passband

Ripple Response

Normalized Frequency (Fs)

0.05

0.1

0.15

0.2

0.25

0.3

0.35

0.4

0.45

0.5

-120

-100

-80

-60

-40

-20

Decb

Passband

Transition Band

Alias Band

Attn Spec

Figure 7-31. Decimation by 32 Complex Frequency

Response

Normalized Frequency (Fs)

0.002

0.004

0.006

0.008

0.01

0.012

0.014

0.016

0.018

0.02

-0.25

-0.245

-0.24

-0.235

-0.23

-0.225

-0.22

-0.215

-0.21

-0.205

-0.2

Decb

Passband

Transition Band

Alias Band

Attn Spec

Figure 7-32. Decimation by 32 Complex Passband

Ripple Response

7.3.4.6 SYNC

The PDN/SYNC pin can be used to synchronize multiple devices using an external SYNC signal. The PDN/

SYNC pin can be configured via SPI (SYNC EN bit) from power down to synchronization functionality, and is

latched in by the rising edge of the sampling clock as shown in Figure 7-33.

CLK

tS,SYNC

tH,SYNC

SYNC

Figure 7-33. External SYNC timing diagram

The synchronization signal is only required when using the decimation filter. Either using the SPI SYNC register

or the PDN/SYNC pin. The internal clock divider is reset and used in the decimation filter. Aligning the internal

clocks as well as I and Q data within the same sample. If no SYNC signal is given, the internal clock dividers are

not synchronized. Leading to a fractional delay across different devices. The SYNC signal also resets the NCO

phase, and loads the new NCO frequency (same as the MIXER RESTART bit).

When trying to resynchronize during operation, the SYNC toggle occurs at 64*K clock cycles, where K is an

integer. This provides a phase continuity of the clock divider.

ADC3683-SP

SBASAB5 – MARCH 2024

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