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ADC3683 Datasheet(PDF) 54 Page - Texas Instruments |
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ADC3683 Datasheet(HTML) 54 Page - Texas Instruments |
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54 / 70 page ![]() Figure 9-5. Register 0x0D (PDN GLOBAL MASK) 7 6 5 4 3 2 1 0 0 0 0 0 MASK CLKBUF MASK REFAMP MASK BG DIS 0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 9-6. Register 0x0D Field Descriptions Bit Field Type Reset Description 7-4 0 R/W 0 Must write 0 3 MASK CLKBUF R/W 0 Global power down mask control for sampling clock input buffer. 0: Clock buffer will get powered down when global power down is exercised. 1: Clock buffer will NOT get powered down when global power down is exercised. 2 MASK REFAMP R/W 0 Global power down mask control for reference amplifier. 0: Reference amplifier will get powered down when global power down is exercised. 1: Reference amplifier is NOT powered down when global power down is exercised. 1 MASK BG DIS R/W 0 Global power down mask control for internal 1.2V bandgap voltage reference. Setting this bit reduces power consumption in global power down mode but increases the wake up time. See the power down option overview. 0: Internal 1.2V bandgap voltage reference is NOT powered down when global power down is exercised. 1: Internal 1.2V bandgap voltage reference is powered down when global power down is exercised. 0 0 R/W 0 Must write 0 ADC3683-SP SBASAB5 – MARCH 2024 www.ti.com 54 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: ADC3683-SP |
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