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ADC3683 Datasheet(PDF) 38 Page - Texas Instruments

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Part # ADC3683
Description  ADC3683-SP Space Grade 18-Bit 1 to 65MSPS, Low Noise, Ultra-low Power Dual Channel ADC
PDF  70 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC3683 Datasheet(HTML) 38 Page - Texas Instruments

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7.3.5.4 Output Interface or Mode Configuration
The following sequence summarizes all the relevant registers for changing the output interface and/or enabling
the decimation filter. Steps 1 and 2 must come first since the E-Fuse load reset the SPI writes, the remaining
steps can come in any order.
Table 7-8. Configuration steps for changing interface or decimation
STEP
FEATURE
ADDRESS
DESCRIPTION
1
Output
Interface
0x07
Select the output interface bit mapping depending on resolution and output interface.
Output Resolution
2-wire
1-wire
1/2-wire
14-bit
0x2B
0x6C
0x8D
16-bit
0x4B
18-bit
0x2B
20-bit
0x4B
2
0x13
Load the output interface bit mapping using the E-fuse loader (0x13, D0). Program register 0x13 to
0x01, wait ~ 1ms so that bit mapping is loaded properly followed by 0x13 0x00
3
0x19
Configure the FCLK frequency based on bypass/decimation and number of lanes used.
Bypass/Dec
SLVDS
FCLK SRC
(D7)
FCLK DIV
(D4)
TOG FCLK
(D0)
Bypass/ Real
Decimation
2-wire
0
1
0
1-wire
0
0
0
1/2-wire
0
0
0
Complex
Decimation
2-wire
1
0
0
1-wire
1
0
0
1/2-wire
0
0
1
4
0x1B
Select the output interface resolution using the bit mapper (D5-D3).
5
0x20
0x21
0x22
Select the FCLK pattern for decimation for proper duty cycle output of the frame clock.
Output Resolution
2-wire
1-wire
1/2-wire
Real Decimation
14-bit
use default
0xFE000
use default
16-bit
0xFF000
18-bit
0xFF800
20-bit
0xFFC00
Complex
Decimation
14-bit
0xFFFFF
0xFFFFF
16-bit
18-bit
20-bit
6
0x39..0x60
0x61..0x88
Change output bit mapping for chA and chB if desired. This works also with the default interface
selection.
7
0x24
0x22
Enable scrambling
8
Decimation
Filter
0x24
Enable the decimation filter
9
0x25
Configure the decimation filter
10
0x2A/B/C/D
0x31/2/3/4
Program the NCO frequency for complex decimation (can be skipped for real decimation)
11
0x27
0x2E
Configure the complex output data stream (set both bits to 0 for real decimation)
SLVDS
OP-Order (D4)
Q-Delay (D3)
2-wire
1
0
1-wire
0
1
1/2-wire
1
1
12
0x26
Set the mixer gain and toggle the mixer reset bit to update the NCO frequency.
ADC3683-SP
SBASAB5 – MARCH 2024
www.ti.com
38
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Copyright © 2024 Texas Instruments Incorporated
Product Folder Links: ADC3683-SP



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