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RT600 Datasheet(PDF) 69 Page - NXP Semiconductors |
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RT600 Datasheet(HTML) 69 Page - NXP Semiconductors |
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69 / 171 page  RT600 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors B.V. 2024. All rights reserved. Product data sheet Rev. 2.2 — 25 January 2024 69 of 173 NXP Semiconductors RT600 Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4 Audio DSP CPUs Fig 7. RT600 clock generation (continued) HS SPI clock select FC14FCLKSEL[2:0] FRG14CTL[15:0] frg_clk14 "none" function clock of HS SPI 48/60m_irc 16m_irc audio_pll_clk mclk_in 011 001 010 000 100 111 Fractional Rate Divider (FRG) HS SPI FRG clock select FRG14CLKSEL[2:0] frg_pll main clk "none" 011 001 010 000 111 48/60m_irc 16m_irc USB clock select USBHSFCLKSEL[2:0] USBHSFCLKDIV USB Clock Divider to HS USB clk_in main_clk 001 111 000 "none" I3C TC Select I3C0FCLKSTCSEL[2:0] I3C0FCLKSTCDIV I3C TC Divider to I3C clk_slow_tc "none" 001 111 000 I3C Clock Select I3C0FCLKSEL[2:0] 48/60m_irc main_clk "none" 001 111 000 I3C0FCLKDIV I3C fclk Divider to I3C fclk (should be a multiple of 24 or 25 MHz) I3C0FCLKSDIV I3C TC Divider to I3C clk_slow 1m_lposc CLKCTL0_PFC1DIV USB PHY bus Clock Divider to USB PHY bus interface main_clk (max. 120 MHz) HS SPI clock select FC15FCLKSEL[2:0] FRG15CTL[15:0] frg_clk15 "none" function clock of PMIC I2C 48/60m_irc 16m_irc audio_pll_clk mclk_in 011 001 010 000 100 111 Fractional Rate Divider (FRG) PMIC I2C FRG clock select FRG15CLKSEL[2:0] frg_pll main clk "none" 011 001 010 000 111 48/60m_irc 16m_irc FLEXSPIFCLKDIV FlexSPI Clock Divider aux0_pll_clk OSPI clock select OSPIFFCLKSEL[2:0] main_pll_clk 48/60m_irc aux1_pll_clk main clk 011 001 010 000 100 111 "none" to FlexSPI fclk SDIO0 Clock Divider to SDIO0 fclk aux0_pll_clk SDIO 0 clock select SDIO0FCLKSEL[2:0] main_pll_clk 48/60m_irc aux1_pll_clk main clk 011 001 010 000 100 111 "none" SDIO0FCLKDIV 200221 SDIO1 Clock Divider to SDIO1 fclk aux0_pll_clk SDIO 1 clock select SDIO1FCLKSEL[2:0] main_pll_clk 48/60m_irc aux1_pll_clk main clk 011 001 010 000 100 111 "none" SDIO1FCLKDIV Flexcomm n clock select FCnFCLKSEL[2:0] 1 per Flexcomm interface (n = 0 through 7) FRGnCTL[15:0] frg_clk n "none" function clock of Flexcomm n 48/60m_irc 16m_irc audio_pll_clk mclk_in 011 001 010 000 100 111 Fractional Rate Divider (FRG) FRG clock select n FRGnCLKSEL[2:0] frg_pll main clk "none" 011 001 010 000 111 48/60m_irc 16m_irc PLL to Flexcomm FRG Divider main_pll_clk FRGPLLCLKDIV frg_pll |
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