RT600 datasheet(79/171 Pages) NXP

79 / 171 page

RT600

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2.2 — 25 January 2024

79 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

• RTS/CTS for hardware signaling for automatic flow control. Software flow control can

be performed using Delta CTS detect, Transmit Disable control, and any GPIO as an

RTS output.

• Received data and status can optionally be read from a single register

• Break generation and detection.

• Receive data is 2 of 3 sample "voting". Status flag set when one sample differs.

• Built-in Baud Rate Generator with auto-baud function.

• A fractional rate divider is shared among all USARTs.

• Interrupts available for Receiver Ready, Transmitter Ready, Receiver Idle, change in

receiver break detect, Framing error, Parity error, Overrun, Underrun, Delta CTS

detect, and receiver sample noise detected.

• Loopback mode for testing of data and flow control.

• In synchronous slave mode, wakes up the part from deep-sleep mode.

• Special operating mode allows operation at up to 9600 baud using the 32.768 kHz

RTC oscillator as the UART clock. This mode can be used while the device is in

deep-sleep mode and can wake-up the device when a character is received.

• USART transmit and receive functions work with the system DMA controller.

10.17.4.5 I2S-bus interface

The I2S bus provides a standard communication interface for streaming data transfer

applications such as digital audio or data collection. The I2S bus specification defines a

3-wire serial bus, having one data, one clock, and one word select/frame trigger signal,

providing single or dual (mono or stereo) audio data transfer as well as other

configurations. In the RT600, the I2S function is included in Flexcomm Interface 6 and

Flexcomm Interface 7. Each of the Flexcomm Interface implements four I2S channel pairs.

The I2S interface within one Flexcomm Interface provides at least one channel pair that

can be configured as a master or a slave. Other channel pairs, if present, always operate

as slaves. All of the channel pairs within one Flexcomm Interface share one set of I2S

signals, and are configured together for either transmit or receive operation, using the

same mode, same data configuration and frame configuration. All such channel pairs can

participate in a time division multiplexing (TDM) arrangement. For cases requiring an

MCLK input and/or output, this is handled outside of the I2S block in the system level

clocking scheme.

Features

• A Flexcomm Interface may implement one or more I2S channel pairs, the first of which

could be a master or a slave, and the rest of which would be slaves. All channel pairs

are configured together for either transmit or receive and other shared attributes. The

number of channel pairs is defined for each Flexcomm Interface, and may be from 0

to 4.

• Configurable data size for all channels within one Flexcomm Interface, from 4 bits to

32 bits. Each channel pair can also be configured independently to act as a single

channel (mono as opposed to stereo operation).

• All channel pairs within one Flexcomm Interface share a single bit clock (SCK) and

word select/frame trigger (WS), and data line (SDA).

RT600 Datasheet(PDF) 79 Page - NXP Semiconductors

RT600 Datasheet(HTML) 79 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL