DSP56374UMSLASHD datasheet(45/64 Pages) FREESCALE

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Enhanced Serial Audio Interface Timing

DSP56374 Data Sheet, Rev. 4.2

Freescale Semiconductor

SCKR edge to FSR out (wl) low

—

17.0

7.0

x ck

i ck a

Data in setup time before SCKR (SCK in

synchronous mode) edge

——

12.0

19.0

—

x ck

i ck

Data in hold time after SCKR edge

—

3.5

9.0

—

x ck

i ck

FSR input (bl, wr) high before SCKR edge 6

——

2.0

12.0

—

x ck

i ck a

FSR input (wl) high before SCKR edge

—

2.0

12.0

—

x ck

i ck a

FSR input hold time after SCKR edge

—

2.5

8.5

—

x ck

i ck a

Flags input setup before SCKR edge

—

0.0

19.0

—

x ck

i ck s

Flags input hold time after SCKR edge

—

6.0

0.0

—

x ck

i ck s

SCKT edge to FST out (bl) high

—

18.0

8.0

x ck

i ck

SCKT edge to FST out (bl) low

—

20.0

10.0

x ck

i ck

SCKT edge to FST out (wr) high6

——

—

20.0

10.0

x ck

i ck

SCKT edge to FST out (wr) low6

——

—

22.0

12.0

x ck

i ck

SCKT edge to FST out (wl) high

—

19.0

9.0

x ck

i ck

SCKT edge to FST out (wl) low

—

20.0

10.0

x ck

i ck

SCKT edge to data out enable from high

impedance

——

—

22.0

17.0

x ck

i ck

SCKT edge to transmitter #0 drive enable

assertion

——

—

17.0

11.0

x ck

i ck

SCKT edge to data out valid

—

18.0

13.0

x ck

i ck

SCKT edge to data out high impedance7

——

—

21.0

16.0

x ck

i ck

Table 24. Enhanced Serial Audio Interface Timing (continued)

No.

Characteristics1, 2, 3

Symbol

Expression3

Min

Max

Condition4

Unit

DSP56374UM/D Datasheet(PDF) 45 Page - Freescale Semiconductor, Inc

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