DSP56374UMSLASHD datasheet(18/64 Pages) FREESCALE

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DSP56374 Data Sheet, Rev. 4.2

Signal Groupings

Freescale Semiconductor

FSR_1

Input or output

GPIO

disconnected

Frame Sync for Receiver_1—This is the receiver frame

sync input/output signal. In the asynchronous mode

(SYN=0), the FSR_1 pin operates as the frame sync input

or output used by all the enabled receivers. In the

synchronous mode (SYN=1), it operates as either the serial

flag 1 pin (TEBE=0), or as the transmitter external buffer

enable control (TEBE=1, RFSD=1).

When this pin is configured as serial flag pin, its direction is

determined by the RFSD bit in the RCCR_1 register. When

configured as the output flag OF1, this pin will reflect the

value of the OF1 bit in the SAICR_1 register, and the data

in the OF1 bit will show up at the pin synchronized to the

frame sync in normal mode or the slot in network mode.

When configured as the input flag IF1, the data value at the

pin will be stored in the IF1 bit in the SAISR_1 register,

synchronized by the frame sync in normal mode or the slot

in network mode.

PE1

Input, output, or

disconnected

Port E1—When the ESAI_1 is configured as GPIO, this

signal is individually programmable as input, output, or

internally disconnected.

The default state after reset is GPIO disconnected.

Internal Pull down resistor.

This input is 5 V tolerant

FST_1

Input or output

GPIO

disconnected

Frame Sync for Transmitter_1—This is the transmitter frame

sync input/output signal. For synchronous mode, this signal

is the frame sync for both transmitters and receivers. For

asynchronous mode, FST_1 is the frame sync for the

transmitters only. The direction is determined by the

transmitter frame sync direction (TFSD) bit in the ESAI_1

transmit clock control register (TCCR_1).

PE4

Input, output, or

disconnected

Port E4—When the ESAI_1 is configured as GPIO, this

signal is individually programmable as input, output, or

internally disconnected.

The default state after reset is GPIO disconnected.

Internal Pull down resistor.

This input is 5 V tolerant.

Table 11. Enhanced Serial Audio Interface_1 Signals (continued)

Signal Name

Signal Type

State during

Reset

Signal Description

DSP56374UM/D Datasheet(PDF) 18 Page - Freescale Semiconductor, Inc

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