DSP56374UMSLASHD datasheet(6/64 Pages) FREESCALE

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DSP56374 Data Sheet, Rev. 4.2

Signal Groupings

Freescale Semiconductor

4.1

Power

4.2

Ground

Dedicated GPIO

Port G3

Table 12

Timer

Table 13

JTAG/OnCE Port

Table 14

Note:

1 Pins are not 5 V. tolerant unless noted.

2 Port H signals are the GPIO port signals which are multiplexed with the MOD and HREQ signals.

3 Port G signals are the dedicated GPIO port signals.

4 Port C signals are the GPIO port signals which are multiplexed with the ESAI signals.

5 Port E signals are the GPIO port signals which are multiplexed with the ESAI_1 signals.

Table 4. Power Inputs

Power Name

Description

PLLA_VDD (1)

PLL Power— The voltage (3.3 V) should be well-regulated and the input should be provided with

an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate

external decoupling capacitors between PLLA_VDD and PLLA_GND. PLLA_VDD requires a filter

as shown in Figure 1 and Figure 2 below. See the DSP56374 technical data sheet for additional

details.

PLLP_VDD(1)

PLL Power— The voltage (3.3 V) should be well-regulated and the input should be provided with

an extremely low impedance path to the 3.3 VDD power rail. The user must provide adequate

external decoupling capacitors between PLLP_VDD and PLLP_GND.

PLLD_VDD (1)

PLL Power— The voltage (1.25 V) should be well-regulated and the input should be provided with

an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate

external decoupling capacitors between PLLD_VDD and PLLD_GND.

CORE_VDD (4)

Core Power—The voltage (1.25 V) should be well-regulated and the input should be provided with

an extremely low impedance path to the 1.25 VDD power rail. The user must provide adequate

external decoupling capacitors.

IO_VDD

(80-pin 4)

(52-pin 3)

SHI, ESAI, ESAI_1, WDT and Timer I/O Power —The voltage (3.3 V) should be well-regulated,

and the input should be provided with an extremely low impedance path to the 3.3 VDD power rail.

This is an isolated power for the SHI, ESAI, ESAI_1, WDT and Timer I/O. The user must provide

adequate external decoupling capacitors.

Table 5. Grounds

Ground Name

Description

PLLA_GND(1)

PLL Ground—The PLL ground should be provided with an extremely low-impedance path to

ground. This connection must be tied externally to all other chip ground connections. The user

must provide adequate external decoupling capacitors between PLLA_VDD and PLLA_GND.

Table 3. DSP56374 Functional Signal Groupings (continued)

Functional Group

Number of

Signals1

Detailed

Description

DSP56374UM/D Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc

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