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56F8335 Datasheet(PDF) 28 Page - Freescale Semiconductor, Inc

Part # 56F8335
Description  16-bit Digital Signal Controller
PDF  160 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

56F8335 Datasheet(HTML) 28 Page - Freescale Semiconductor, Inc

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56F8335 Technical Data, Rev. 5
28
Freescale Semiconductor
Preliminary
PWMA0
58
Output
In reset,
output is
disabled,
pull-up is
enabled
PWMA0 - 5 — These are six PWMA output pins.
PWMA1
60
PWMA2
61
PWMA3
63
PWMA4
64
PWMA5
66
ISA0
(GPIOC8)
104
Schmitt
Input
Schmitt
Input/
Output
Input,
pull-up
enabled
ISA0 - 2 — These three input current status pins are used for
top/bottom pulse width correction in complementary channel
operation for PWMA.
Port C GPIO — These GPIO pins can be individually
programmed as input or output pins.
In the 56F8335, these pins default to ISA functionality.
In the 56F8135, the default state is not one of the functions
offered and must be reconfigured.
To deactivate the internal pull-up resistor, clear the appropriate
bit of the GPIOC_PUR register. See Part 6.5.6 for details.
ISA1
(GPIOC9)
105
ISA2
(GPIOC10)
106
FAULTA0
67
Schmitt
Input
Input,
pull-up
enabled
FAULTA0 - 2 — These three fault input pins are used for
disabling selected PWMA outputs in cases where fault conditions
originate off-chip.
To deactivate the internal pull-up resistor, set the PWMA0 bit in
the SIM_PUDR register. See Part 6.5.6 for details.
FAULTA1
68
FAULTA2
69
FAULTA3
70
Schmitt
Input
Input,
pull-up
enabled
FAULTA3 — This fault input pin is used for disabling selected
PWMA outputs in cases where fault conditions originate off-chip.
To deactivate the internal pull-up resistor, set the PWMA1 bit in
the SIM_PUDR register. See Part 6.5.6 for details.
PWMB0
32
Output
In reset,
output is
disabled,
pull-up is
enabled
PWMB0 - 5 — Six PWMB output pins.
PWMB1
33
PWMB2
34
PWMB3
37
PWMB4
38
PWMB5
39
Table 2-2 Signal and Package Information for the 128-Pin LQFP (Continued)
Signal
Name
Pin No.
Type
State
During
Reset
Signal Description



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