56F8335 datasheet(77/160 Pages) FREESCALE

77 / 160 page

56F8335 Technical Data, Rev. 5

Freescale Semiconductor

Preliminary

5.6.2.1

Reserved—Bits 15–6

This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.

5.6.2.2

EOnCE Receive Register Full Interrupt Priority Level

(RX_REG IPL)—Bits 5–4

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.

It is disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 1

•

10 = IRQ is priority level 2

•

11 = IRQ is priority level 3

5.6.2.3

EOnCE Transmit Register Empty Interrupt Priority Level

(TX_REG IPL)—Bits 3–2

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.

It is disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 1

•

10 = IRQ is priority level 2

•

11 = IRQ is priority level 3

5.6.2.4

EOnCE Trace Buffer Interrupt Priority Level (TRBUF IPL)—

Bits 1–0

This field is used to set the interrupt priority level for IRQs. This IRQ is limited to priorities 1 through 3.

It is disabled by default.

•

00 = IRQ disabled (default)

•

01 = IRQ is priority level 1

•

10 = IRQ is priority level 2

•

11 = IRQ is priority level 3

56F8335 Datasheet(PDF) 77 Page - Freescale Semiconductor, Inc

56F8335 Datasheet(HTML) 77 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL