OXCF950 datasheet(8/66 Pages) OXFORD

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OXCF950 rev B DATA SHEET

OXFORD SEMICONDUCTOR, INC.

3 PIN DESCRIPTIONS

TQFP Pin Number (TFBGA ball)

Dir1

Name

Description

CF/PCMCIA Interface and Control

46, 45, 43, 42

(D4, A2, A3, B3)

A[3:0]

PCMCIA/CF address bus, bits [3:0]

6, 7, 10, 11, 12, 37, 38, 41

(E2, E1, F1, F3, G1, A6, B5, A4)

I/O

D[7:0]

PCMCIA/CF data bi-directional bus.

44 (C3)

REG#

5 (D1)

CE[1]#

Active low card enable

4 (D2)

OE#

Active low memory read enable

1 (B1)

WE#

Active-low write enable used for strobing Memory Write data

(Attribute memory).

3 (C1)

IORD#

Active-low I/O read enable

2 (C2)

IOWR#

Active-low I/O write enable

32 (C5)

IOIS16#

INT

Write protect (in Memory only mode)

Data is 16 bit (in IO and Memory mode)

C950 Mode:Active-high interrupt request

47 (B2)

RESET

PCMCIA/CF Reset

48 (A1)

READY#

IREQ#

Device ready (in Memory only mode)

Active-low Interrupt request (in C950, IO and Memory mode).

UART / Local Bus Function

24 (H6)

SOUT

IrDA_Out

UART serial data output.

UART IrDA data output when MCR[6] is set in enhanced

mode.

23 (G5)

SIN

IrDA_In

UART serial data input.

UART IrDA data input when IrDA mode is enabled (see

above).

29 (E6)

DCD#

Active-low modem data-carrier-detect input.

26 (F5)

DTR#

485_En

Tx_Clk_Out

Active-low modem data-terminal-ready output. If automated

DTR# flow control is enabled, the DTR# pin is asserted and

de-asserted if the receiver FIFO reaches or falls below the

programmed thresholds, respectively.

In RS485 half-duplex mode, the DTR# pin may be

programmed to reflect the state of the transmitter empty bit to

automatically control the direction of the RS485 transceiver

buffer (see register ACR[4:3]).

Transmitter 1x clock (baud rate generator output). For

isochronous applications, the 1x (or Nx) transmitter clock may

be asserted on the DTR# pin (see register CKS[5:4]).

25 (G6)

RTS#

Active–low modem request-to-send output. If automated

RTS# flow control is enabled, the RTS# pin is de-asserted

and reasserted whenever the receiver FIFO reaches or falls

below the programmed thresholds, respectively.

27 (F6)

CTS#

Active-low modem clear-to-send input. If automated CTS#

flow control is enabled, upon de-assertion of the CTS# pin,

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