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MPC5200B Datasheet(PDF) 30 Page - Freescale Semiconductor, Inc |
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MPC5200B Datasheet(HTML) 30 Page - Freescale Semiconductor, Inc |
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30 / 78 page  MPC5200B Data Sheet, Rev. 1 Electrical and Thermal Characteristics Freescale Semiconductor 30 3.3.7.3 MUXed Mode NOTES:S 1. ACK can shorten the CS pulse width. Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified from 0 - 65535. 2. ACK is input and can be used to shorten the CS pulse width. 3. Deadcycles are only used, if no arbitration to an other module (ATA or PCI) of the shared local bus happens. If arbitration happens the bus can be driven within 4 IPB clocks by an other modules. Table 26. MUXed Mode Timing Sym Description Min Max Units Notes SpecID tCSA PCI CLK to CS assertion 4.6 10.6 ns A7.39 tCSN PCI CLK to CS negation 2.9 7.0 ns A7.40 tALEA PCI CLK to ALE assertion - 3.6 ns A7.41 t1 ALE assertion before Address, Bank, TSIZ assertion - 5.7 ns A7.42 t2 CS assertion before Address, Bank, TSIZ negation - -1.2 ns A7.43 t3 CS assertion before Data wr valid - -1.2 ns A7.44 t4 Data wr hold after CS negation tIPBIck - ns A7.45 t5 Data rd setup before CS negation 8.5 - ns A7.46 t6 Data rd hold after CS negation 0 (DC+1)*tPCIck ns (1),(3) A7.47 t7 ALE pulse width - tPCIck ns A7.48 tTSA CS assertion after TS assertion - 6.9 ns A7.49 t8 TS pulse width - tPCIck ns A7.50 t9 CS pulse width (2+WS)*tPCIck (2+WS)*tPCIck ns A7.51 tOEA OE assertion before CS assertion - 4.7 ns A7.52 tOEN OE negation before CS negation - 5.9 ns A7.53 t10 RW assertion before ALE assertion tIPBIck - ns A7.54 t11 RW negation after CS negation - tPCIck ns A7.55 t12 ACK assertion after CS assertion tIPBIck -ns (2) A7.56 t13 ACK negation after CS negation - tPCIck ns (2) A7.57 t14 ALE negation to CS assertion - tPCIck ns A7.58 t15 ACK change before PCI clock - 2.0 ns (2) A7.59 t16 ACK change after PCI clock - 4.4 ns (2) A7.60 |
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