MPC5200B datasheet(42/78 Pages) FREESCALE

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MPC5200B Data Sheet, Rev. 1

Electrical and Thermal Characteristics

Freescale Semiconductor

Figure 27. Ethernet Timing Diagram—MII Rx Signal

Figure 28. Ethernet Timing Diagram—MII Tx Signal

Table 32. MII Tx Signal Timing

Sym

Description

Min

Max

Unit

SpecID

TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER

invalid

5—

A9.5

TX_CLK rising edge to TXD[3:0], TX_EN, TX_ER valid

—

A9.6

TX_CLK pulse width high

35%

65%

TX_CLK Period(1)

NOTES:

The TX_CLK frequency shall be 25% of the nominal transmit frequency, e.g., a PHY operating at 100 Mb/s must

provide a TX_CLK frequency of 25 MHz and a PHY operating at 10 Mb/s must provide a TX_CLK frequency of 2.5

MHz. See the IEEE 802.3 Specification [6].

A9.7

TX_CLK pulse width low

35%

65%

TX_CLK Period(1)

A9.8

Table 33. MII Async Signal Timing

Sym

Description

Min

Max

Unit

SpecID

CRS, COL minimum pulse width

1.5

—

TX_CLK Period

A9.9

RX_CLK (Input)

RXD[3:0] (inputs)

RX_DV

RX_ER

TX_CLK (Input)

TXD[3:0] (Outputs)

TX_EN

TX_ER

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