M24256E-FDW6TP datasheet(23/46 Pages) STMICROELECTRONICS

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6.7

Read operations on configurable device address register

Following a start condition the bus master sends a device select code with the RW bit (RW) set to 0. The device

acknowledges this and waits for the address bytes where the CDA register is located. The device responds to

each address byte with an acknowledge bit. Then, the bus master sends another start condition, and repeats the

device select code,with the RW bit set to 1. The device acknowledges this, and outputs the contents of the CDA

device address register.

To terminate the stream of data byte, the bus master must not acknowledge the byte, and must generate a stop

condition, as shown in Figure 15.

After the successful completion of a read configurable device address, the device internal address counter is

not incremented by one, to point to the next byte address. Reading more than one byte loops on reading the

configurable device address register value.

The configurable device address register cannot be read while a write cycle (tW) is ongoing.

The configurable device address bits (C2, C1, C0) values can be checked by sending the device select code.

•

If the chip enable address bit 3, bit 2, bit 1 sent in the device select code is matching with the C2, C1 and

C0 values, the device sends an ACK

•

Otherwise, device will answer no ACK

Figure 15. Random read on configuration device address register

Dev sel

Byte addr

Data out

ACK

NO ACK

ACK

Dev sel

* The seven most significant bits of the first device select code of a random read must be identical to the seven

most significant bits of the second device select code

M24256E-F

Read operations on configurable device address register

DS12687 - Rev 3

page 23/46

M24256E-FDW6TP Datasheet(PDF) 23 Page - STMicroelectronics