Full-Bridge PWM Gate Driver

A89505

6

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

Control Logic

IN1

IN2

SLEEPn

10 × VSENSE >

VREF

OUTA

OUTB

Function

x

x

0

x

Z

Z

Standby Mode

0

0

1

x

Z

Z

Coast

0

1

1

false

L

H

Reverse

1

0

1

false

H

L

Forward

1

1

1

x

L

L

Slow Decay SR (Brake)

0

1

1

true

H/L

L

Internal Chop Reverse, Mixed Decay *

1

0

1

true

L

H/L

Internal Chop Forward, Mixed Decay *

* In fast decay, outputs change to high-Z state when load current approaches zero, to prevent reversal of current.

I= V/

OCL

REF

SENSE

R/ 10

I_OUT

OCLn

t

OCLn

OCLn Output Flag

OCLn output function is described in the Functional Description section.

AA

BB

C

300 µs

AIOUT

V

SENSE

IN1

(IN2 = High)

0 V

0 V

V= VREF /10

SENSE

AIOUT Output

A. Internal OCL chop. AIOUT holds while SENSE voltage varies during the mixed-decay off-time.

B. INx chop. AIOUT holds while SENSE voltage drops to 0 V during slow decay.

C. Slow-decay timeout. AIOUT is forced to 0 V 300 µs after ENABLE goes low.