Full-Bridge PWM Gate Driver

A89505

12

Allegro MicroSystems

955 Perimeter Road

Manchester, NH 03103-3353 U.S.A.

www.allegromicro.com

For Reference Only – Not for Tooling Use

(Reference JEDEC MO-153ACT; Allegro DWG-0000379, Rev. 3)

NOTTO SCALE

Dimensions in millimeters

Dimensions exclusive of mold flash, gate burrs, and dambar protrusions

Exact case and lead configuration at supplier discretion within limits shown

A

1.20 MAX

0.15

0.025

0.30

0.19

0.20

0.09

8°

0°

0.60 ±0.15

1.00 REF

C

SEATING

PLANE

C

0.10

20X

0.65 BSC

0.25 BSC

2

1

1

20

6.50 ±0.10

4.40 ±0.10

3.00

3.00

4.20

4.20

6.40 ±0.20

GAUGE PLANE

SEATING PLANE

A

B

0.45

1.70

20

2

1

B

6.10

0.65

C Exposed thermal pad (bottom surface)

C

PCB Layout Reference View

Terminal #1 mark area

Reference land pattern layout (reference IPC7351 SOP65P640X110-21M); all pads a minimum of 0.20 mm from all adjacent pads;

adjust as necessary to meet application process requirements and PCB layout tolerances; when mounting on a multilayer PCB,

thermal vias at the exposed thermal pad land can improve thermal dissipation (reference EIA/JEDEC Standard JESD51-5)

Branding scale and appearance at supplier discretion

D

XXXXXXX

Date Code

Lot Number

D

Standard Branding Reference View

Lines 1, 2, 3 = 8 characters

Line 1: Part Number

Line 2: Logo A, 4 digit Date Code

Line 3: Characters 5, 6, 7, 8 of Assembly Lot Number

LP Package, 20-Pin eTSSOP with Exposed Thermal Pad