SCF5249VM140 datasheet(18/56 Pages) FREESCALE

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SCF5249 Integrated ColdFire® Microprocessor Data Sheet, Rev. 3

Signal Descriptions

Freescale Semiconductor

8.4

SDRAM Controller Signals

The following SDRAM signals provide a seamless interface to external SDRAM. An SDRAM width of

16 bits is supported and can access as much as 64 Mybtes of memory. ADRAMs are not supported.

NOTE

The SDRAM_CS2 signal is only used on the 160 MAPBGA package.

8.5

Chip Selects

There are two chip select outputs on the SCF5249 device. CS0 and CS1/GPIO58. The second signal is

multiplexed with a GPIO signal. The active low chip selects can be used to access asynchronous memories.

The interface is glueless.

8.6

ISA Bus

The SCF5249 supports an ISA bus. (No ISA DMA channel). Using the ISA bus protocol, reads and writes

to up to two ISA bus peripherals are possible. For the first peripheral, CS2/IDE-DIOR/GPIO13 and

IDE-DIOW/GPIO14 are the read and write strobe. For the second peripheral, CS3/SRE/GPIO11 and

SWE/GPIO12 are the read and write strobe. Either peripheral can insert wait states by pulling

IDE-IORDY/GPIO16

Table 5. SDRAM Controller Signals

SDRAM Signal

Description

Synchronous DRAM row address strobe

The SDRAS active low pin provides a seamless interface to the RAS

input on synchronous DRAM

Synchronous DRAM Column Address

Strobe

The SDCAS active low pin provides a seamless interface to CAS input

on synchronous DRAM.

Synchronous DRAM Write

The SDWE active-low pin is asserted to signify that a SDRAM write

cycle is underway. This pin outputs logic ‘1’ during read bus cycles.

Synchronous DRAM Chip Enable

The SD_CS1 and The SDRAM_CS2/GPIO7 active-low output signal is

used during synchronous mode to route directly to the chip select of up

to two SDRAM devices.

The SDRAM_CS2/gpio7 can be programmed to be gpio using

the GPIO-FUNCTION register.

Synchronous DRAM UDQM and LQDM

signals

The DRAM byte enables UDMQ and LDQM are driven by the

SDUDQM and SDLDQM byte enable outputs.

Synchronous DRAM clock

The DRAM clock is driven by the SCLK signal

Synchronous DRAM Clock Enable

The BCLKE active high output signal is used during synchronous

mode to route directly to the SCKE signal of external SDRAMs. This

signal provides the clock enable to the SDRAM.

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