LTM8024 datasheet(18/32 Pages) AD

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LTM4703

Rev. 0

For more information www.analog.com

Synchronization

To synchronize the LTM4703 oscillator to an external fre-

quency, connect a square wave (with about 20% to 80%

duty cycle) to the SYNC pin. The square wave amplitude

should have valleys, which are below 0.4V and peaks

above 1.5V, with a minimum on-time and off-time of 50ns.

The LTM4703 runs in FCM to maintain regulation while

synchronized to an external clock. The LTM4703 may

be synchronized over a 300kHz to 3MHz range. The RT

resistor should be chosen to set the LTM4703 switching

frequency to below the lowest synchronization input by

approximately 20%. For example, if the synchronization

signal is 500kHz or higher, the RT should be selected

for 400kHz.

Minimum Frequency for High-Duty Cycle

For duty cycles greater than 50% (VOUT/VIN > 0.5), a

minimum frequency is required to avoid sub-harmonic

oscillation. Refer to the Analog Devices Application Note

19. Equation 6 calculates the minimum frequency.

fSW 2 • VOUT – VIN

(6)

where VOUT is the output voltage, VIN is the input voltage,

and fSW is the switching frequency in MHz.

Example:

VIN = 8V, VOUT = 6V, fSW = 1MHz

Programmable Power Good

LTM4703 features a programmable power good by

using a single resistor across the VOUT pin and PGSET

pin as shown in Equation 7.

VOUT(PG_THRESHOLD) = 0.5V •

49.9k

• RPGSET

IPGSET

RPGSET

(7)

If the PGSET pin increases above 537.5mV or decreases

below 462.5mV, the open-drain PG pin de-asserts and

becomes high impedance. The power good comparator

has 2mV hysteresis. The PGSET pin current (IPGSET) from

the Electrical Characteristics table must be considered

when determining the resistor value. Note that the pro-

grammable power good and fast start-up capabilities are

disabled when PGSET is connected to 0.5V or when the

device is shutdown. Table 3 suggests some 1% RPGSET

resistor values for common VOUT configurations.

Table 3. Suggested RPGSET Resistor Values

VOUT

(V)

RPGSET

(kΩ)

0.3

Open

(Externally Inject 0.5V to the PGSET Pin)

0.5

0.8

30.1

0.9

40.2

49.9

1.2

69.8

1.5

100

1.8

130

2.5

200

3.3

280

5.0

453

6.0

549

Negative Output

The LTM4703 can generate a negative output voltage by

connecting its VOUT to system GND and the LTM4703 GND

to the negative voltage rail. Examples of this are shown in

Figure 15 and Figure 16 in the Typical Applications section.

The most versatile way to generate a negative output is

to use a dedicated regulator, which was designed to gen-

erate a negative voltage. Using a buck regulator like the

LTM4703 to generate a negative voltage is a simple and

cost-effective solution, as long as certain restrictions are

taken especially, VIN + |VOUT| ≤ 16V. Refer to the Analog

Devices Design Note 1021 (DN1021) for more details on

generating negative output.

Figure 2 shows a typical negative output voltage appli-

cation. Note that LTM4703 VOUT is connected to system

GND, and input power is applied from VIN to LTM4703’s

VOUT. As a result, the LTM4703 does not behave as a

APPLICATIONS INFORMATION

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