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M58LT128HST Datasheet(PDF) 68 Page - STMicroelectronics |
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M58LT128HST Datasheet(HTML) 68 Page - STMicroelectronics |
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68 / 110 page  DC and AC parameters M58LT128HST, M58LT128HSB 68/110 Table 25. Write ac Characteristics, Chip Enable Controlled(1) 1. Sampled only, not 100% tested. Symbol Alt Parameter M58LT128HST/B Unit 85 tAVAV tWC Address Valid to Next Address Valid Min 85 ns tAVEH Address Valid to Chip Enable High Min 50 ns tAVLH Address Valid to Latch Enable High Min 10 ns tDVEH tDS Data Valid to Chip Enable High Min 50 ns tEHAX tAH Chip Enable High to Address Transition Min 0 ns tEHDX tDH Chip Enable High to Input Transition Min 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low Min 25 ns tEHGL Chip Enable High to Output Enable Low Min 0 ns tEHWH tCH Chip Enable High to Write Enable High Min 0 ns tELKV Chip Enable Low to Clock Valid Min 9 ns tELEH tCP Chip Enable Low to Chip Enable High Min 50 ns tELLH Chip Enable Low to Latch Enable High Min 10 ns tELQV Chip Enable Low to Output Valid Min 85 ns tGHEL Output Enable High to Chip Enable Low Min 17 ns tLHAX Latch Enable High to Address Transition Min 9 ns tLLLH Latch Enable Pulse Width Min 10 ns tWHEL (2) 2. tWHEL has this value when reading in the targeted bank or when reading following a Set Configuration Register command. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command is a Read Array operation in a different bank and no changes to the Configuration Register have been issued, tWHEL is 0ns. Write Enable High to Chip Enable Low Min 25 ns tWLEL tCS Write Enable Low to Chip Enable Low Min 0 ns tEHVPL Chip Enable High to VPP Low Min 200 ns tQVVPL Output (Status Register) Valid to VPP Low Min 0 ns tVPHEH tVPS VPP High to Chip Enable High Min 200 ns |
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