TUSB2E221 datasheet(29/65 Pages) TI

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1. The host initiates a write operation by generating a start condition (S), followed by the TUSB2E221 7-bit

address and a zero-value “W/R” bit to indicate a write cycle.

2. The TUSB2E221 acknowledges the address cycle.

3. The host presents the register offset within the TUSB2E221 to be written, consisting of one byte of data,

MSB-first.

4. The TUSB2E221 acknowledges the sub-address cycle.

5. The host presents the first byte of data to be written to the I2C register.

6. The TUSB2E221 acknowledges the byte transfer.

7. The host may continue presenting additional bytes of data to be written, with each byte transfer completing

with an acknowledge from the TUSB2E221.

8. The host terminates the write operation by generating a stop condition (P).

Figure 8-6. I2C Read Without Repeated Start

Use this procedure to read the TUSB2E221 I2C registers without a repeated Start (refer Figure 8-6).

1. The host initiates a read operation by generating a start condition (S), followed by the TUSB2E221 7-bit

address and a zero-value “W/R” bit to indicate a read cycle.

2. The TUSB2E221 acknowledges the 7-bit address cycle.

3. Following the acknowledge the host continues sending clock.

4. The TUSB2E221 transmit the contents of the memory registers MSB-first starting at register 00h or last read

the register offset specified in the write.

5. The TUSB2E221 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the host after

each byte transfer; the I2C host acknowledges reception of each data byte transfer.

6. If an ACK is received, the TUSB2E221 transmits the next byte of data as long as host provides the clock. If a

NAK is received, the TUSB2E221 stops providing data and waits for a stop condition (P).

7. The host terminates the write operation by generating a stop condition (P).

Figure 8-7. I2C Read with Repeated Start

Use this procedure to read the TUSB2E221 I2C registers with a repeated Start (refer Figure 8-7).

1. The host initiates a read operation by generating a start condition (S), followed by the TUSB2E221 7-bit

address and a zero-value “W/R” bit to indicate a write cycle.

2. The TUSB2E221 acknowledges the 7-bit address cycle.

3. The host presents the register offset within the TUSB2E221 to be written, consisting of one byte of data,

MSB-first.

4. The TUSB2E221 acknowledges the register offset cycle.

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TUSB2E221

SNLS757B – JUNE 2024 – REVISED NOVEMBER 2024

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TUSB2E221 Datasheet(PDF) 29 Page - Texas Instruments