TUSB2E221 datasheet(31/65 Pages) TI

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9 Register Map

9.1 TUSB2E221 Registers

Table 9-1 lists the memory-mapped registers for the TUSB2E221 registers. All register offset addresses not

listed in Table 9-1 should be considered as reserved locations and the register contents should not be modified.

Table 9-1. TUSB2E221 Registers

Offset

Acronym

Section

GPIO0_CONFIG

RAP Register for Port 0 (Write = 0h, Read = 30h)

10h

LOPWR_N_UART_P0

20h

CONFIG_PORT0

RAP Register for Port 0 (Write = 20h, Read = 10h)

30h

U_TX_ADJUST_PORT0

RAP Register for Port 0 (Write = 30h, Read = 0h), Default

through OTP

31h

U_HS_TX_PRE_EMPHASIS_P0

RAP Register for Port 0 (Write = 31h, Read = 1h), Default

through OTP

32h

U_RX_ADJUST_PORT0

RAP Register for Port 0 (Write = 32h, Read = 2h), Default

through OTP

33h

U_DISCONNECT_SQUELCH_PORT0

RAP Register for Port 0 (Write = 33h, Read = 3h), Default

through OTP

37h

E_HS_TX_PRE_EMPHASIS_P0

RAP Register for Port 0 (Write = 37h, Read = 7h), Default

through OTP

38h

E_TX_ADJUST_PORT0

RAP Register for Port 0 (Write = 38h, Read = 8h), Default

through OTP

39h

E_RX_ADJUST_PORT0

RAP Register for Port 0 (Write = 39h, Read = 9h), Default

through OTP

40h

GPIO1_CONFIG

RAP Register for Port 1 (Write = 0h, Read = 30h)

50h

LOPWR_N_UART_P1

60h

CONFIG_PORT1

RAP Register for Port 1 (Write = 20h, Read = 10h)

70h

U_TX_ADJUST_PORT1

RAP Register for Port 1 (Write = 30h, Read = 0h), Default

through OTP

71h

U_HS_TX_PRE_EMPHASIS_P1

RAP Register for Port 1 (Write = 31h, Read = 1h), Default

through OTP

72h

U_RX_ADJUST_PORT1

RAP Register for Port 1 (Write = 32h, Read = 2h), Default

through OTP

73h

U_DISCONNECT_SQUELCH_PORT1

RAP Register for Port 1 (Write = 33h, Read = 3h), Default

through OTP

77h

E_HS_TX_PRE_EMPHASIS_P1

RAP Register for Port 1 (Write = 37h, Read = 7h), Default

through OTP

78h

E_TX_ADJUST_PORT1

RAP Register for Port 1 (Write = 38h, Read = 8h), Default

through OTP

79h

E_RX_ADJUST_PORT1

RAP Register for Port 1 (Write = 39h, Read = 9h), Default

through OTP

A3h

INT_STATUS_1

A4h

INT_STATUS_2

B0h

REV_ID

B2h

GLOBAL_CONFIG

B3h

INT_ENABLE_1

B4h

INT_ENABLE_2

Complex bit access types are encoded to fit into small table cells. Table 9-2 shows the codes that are used for

access types in this section.

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TUSB2E221

SNLS757B – JUNE 2024 – REVISED NOVEMBER 2024

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