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TUSB2E221 Datasheet(PDF) 19 Page - Texas Instruments |
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TUSB2E221 Datasheet(HTML) 19 Page - Texas Instruments |
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19 / 65 page  MIN NOM MAX UNIT tSU_DAT Data input or False start/stop, setup time, SCL (Tr=72ns to 120ns), SDA (Tf=6.5ns to 81.5ns), 1MHz FM+ 50 ns tHD_DAT Data input or False start/stop, hold time, SCL (Tr=72ns to 120ns), SDA (Tf=6.5ns to 81.5ns), 1MHz FM+ 0 ns tVD_DAT, tVD_ACK SDA output delay, SCL (Tr=72ns to 120ns), SDA (Tf=6.5ns to 81.5ns), 1MHz FM+ 20 450 ns tHD_DAT_SL Data hold time when device is transmitting 6.67 ns tSP Glitch width suppressed 50 91 ns tBUF Bus free time between a STOP and START condition (host minimum spec that device must tolerate) 0.5 µs tLOW Low Period for SCL clock (host minimum spec that device must tolerate) 0.5 µs tHIGH High Period for SCL clock (host minimum spec that device must tolerate) 0.26 µs I2C (FM) tSU_STO Stop setup time, SCL (Tr=180ns to 300ns), SDA (Tf=6.5ns to 106.5ns), 400kHz FM 600 ns tHD_STA Start hold time, SCL (Tr=180ns to 300ns), SDA (Tf=6.5ns to 106.5ns), 400kHz FM 600 ns tSU_STA Start setup time, SCL (Tr=180ns to 300ns), SDA (Tf=6.5ns to 106.5ns), 400kHz FM 600 ns tSU_DAT Data input or False start/stop, setup time, SCL (Tr=180ns to 300ns), SDA (Tf=6.5ns to 106.5ns), 400kHz FM 100 ns tHD_DAT Data input or False start/stop, hold time, SCL (Tr=180ns to 300ns), SDA (Tf=6.5ns to 106.5ns), 400kHz FM 0 ns tVD_DAT, tVD_ACK SDA output delay, SCL (Tr=180ns to 300ns), SDA (Tf=6.5ns to 106.5ns), 400kHz FM 20 900 ns tHD_DAT_SL Data hold time when device is transmitting 13.5 ns tSP Glitch width suppressed 50 91 ns tBUF Bus free time between a STOP and START condition (host minimum spec that device must tolerate) 1.3 µs tLOW Low Period for SCL clock (host minimum spec that device must tolerate) 1.3 µs tHIGH High Period for SCL clock (host minimum spec that device must tolerate) 0.6 µs I2C (STD) tSU_STO Stop setup time, SCL (Tr=600ns to 1000ns), SDA (Tf=6.5ns to 106.5ns), 100kHz STD 4 µs tHD_STA Start hold time, SCL (Tr=600ns to 1000ns), SDA (Tf=6.5ns to 106.5ns), 100kHz STD 4 µs tSU_STA Start setup time, SCL (Tr=600ns to 1000ns), SDA (Tf=6.5ns to 106.5ns), 100kHz STD 4.7 µs tSU_DAT Data input or False start/stop, setup time, SCL (Tr=600ns to 1000ns), SDA (Tf=6.5ns to 106.5ns), 100kHz STD 250 ns tHD_DAT Data input or False start/stop, hold time, SCL (Tr=600ns to 1000ns), SDA (Tf=6.5ns to 106.5ns), 100kHz STD 5 µs tVD_DAT, tVD_ACK SDA output delay, SCL (Tr=600ns to 1000ns), SDA (Tf=6.5ns to 106.5ns), 100kHz STD 3.45 µs tHD_DAT_SL Data hold time when device is transmitting 13.5 ns tSP Glitch width suppressed 50 91 ns tBUF Bus free time between a STOP and START condition (host minimum spec that device must tolerate) 4.7 µs tLOW Low Period for SCL clock (host minimum spec that device must tolerate) 4.7 µs www.ti.com TUSB2E221 SNLS757B – JUNE 2024 – REVISED NOVEMBER 2024 Copyright © 2024 Texas Instruments Incorporated Submit Document Feedback 19 Product Folder Links: TUSB2E221 |
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