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TUSB2E221 Datasheet(PDF) 34 Page - Texas Instruments |
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TUSB2E221 Datasheet(HTML) 34 Page - Texas Instruments |
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34 / 65 page  Table 9-4. LOPWR_N_UART_P0 Register Field Descriptions (continued) Bit Field Type Reset Default from OTP (Y/N) Description 1 UART_en_by_reg_not_ pin_P0 RH/W 0h Y Select whether UART mode is enabled by register or by GPIO0 pin Default through OTP 0h = select UART_mode_en_P0 register to enable UART mode 1h = select GPIO0 pin to enable UART mode 0 UART_mode_en_P0 RH/W 0h Y If GPIO0 is not selected to enable UART mode, this register will enable it. Default through OTP 0h = disable UART mode between eUSB2 and USB 2.0 pins 1h = enable UART mode between eUSB2 and USB 2.0 pins 9.1.3 CONFIG_PORT0 Register (Offset = 20h) [Reset = 00h] CONFIG_PORT0 is shown in Table 9-5. Return to the Summary Table. Table 9-5. CONFIG_PORT0 Register Field Descriptions Bit Field Type Reset Description 7 RESERVED R/W 0h Reserved 6-5 RESERVED R 0h Reserved 4-3 HOST_DEVICE_P0 RH 0h Port0 is configured as a Host repeater or a Device repeater 0h = Not configured 1h = Host repeater 2h = Device repeater 3h = Reserved 2-1 RESERVED R 0h Reserved 0 CDP_2_STATUS_P0 RH 0h Primary detection detected on port0 if CDP_2_EN_P0=1 0h = CDP primary detection detected 1h = CDP primary detection not detected 9.1.4 U_TX_ADJUST_PORT0 Register (Offset = 30h) [Reset = 77h] U_TX_ADJUST_PORT0 is shown in Table 9-6. Return to the Summary Table. Hardware default value can be overridden through factory programmable OTP for this register. Table 9-6. U_TX_ADJUST_PORT0 Register Field Descriptions Bit Field Type Reset Default from OTP (Y/N) Description 7-6 U_HS_TERM_P0 RH/W 1h Y ZHSTERM adjustment USB HS Termination Adjustment (-5% to 10% in 5% steps) Default through OTP 0h = 42.75 Ω (typical) 1h = 45 Ω (typical) (hw default) 2h = 47.25 Ω (typical) 3h = 49.5 Ω (typical) TUSB2E221 SNLS757B – JUNE 2024 – REVISED NOVEMBER 2024 www.ti.com 34 Submit Document Feedback Copyright © 2024 Texas Instruments Incorporated Product Folder Links: TUSB2E221 |
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