TUSB2E221 datasheet(26/65 Pages) TI

26 / 65 page

8.4.7 GPIO Mode

8.4.7.1 EQ0 as GPIO0

The EQ0 pin enters input mode at power up and is sampled during reset.

The EQ0 defaults to active high UART mode (bypass mode) enable control for eUSB2 port0 after power up in

I2C mode.

The EQ0 pin can be configured to be input or output mode through the I2C register write. The output event is

selected through the I2C register. Refer to the GPIO0_CONFIG register for more information.

The EQ0 input status change can be reported through the EQ2/INT as an interrupt if enabled through the I2C.

The status change trigger can be programmed to be edge trigger or level trigger through the I2C.

The EQ0 pin in output mode defaults to open-drain output but can be configured to be push-pull output. The

EQ0 pin can drive up to 3pF loads when in push-pull mode.

The EQ0 pin reverts back to input upon RESETB assert, deassert, or soft reset.

In non I2C mode, the EQ0 pin is used for USB PHY tuning.

8.4.7.2 EQ1 as GPIO1

The EQ1 pin enters input mode at power up and is sampled during reset.

The EQ1 defaults to active high UART mode (bypass mode) enable control for eUSB2 port1 after power up in

I2C mode.

The EQ1 pin can be configured to be input or output mode through the I2C register write. The output event is

selected through the I2C register. Refer to the GPIO1_CONFIG register.

The EQ1 input status change can be reported through the EQ2/INT as an interrupt if enabled through the I2C.

The status change trigger can be programmed to be an edge trigger or level trigger through the I2C.

The EQ1 pin in output mode defaults to open-drain output but can be configured to be push-pull output. EQ1 pin

can drive up to 3pF loads when in push-pull mode.

The EQ1 pin reverts back to input upon RESETB assert, deassert, or soft reset.

In non I2C mode, the EQ1 pin is used for USB PHY tuning.

8.4.7.3 EQ2/INT as GPIO2

The EQ2/INT pin defaults to open-drain interrupt (INT) active low output at power up but can be programmed

through the I2C to be a push-pull output. In push-pull mode, the EQ2/INT pin can be programmed to be either

active high or active low. Interrupt output is a level-sensitive interrupt. Trigger events can be selected through the

I2C.

Connect EQ2/INT to APU to use interrupt functions and a pullup resistor (open-drain mode).

EQ2/INT interrupt output can be configured through the INT_ENABLE_1/2 and INT_STATUS_1/2 registers.

In non I2C mode, EQ2/INT pin is used for USB PHY tuning.

8.4.8 CROSS

The CROSS pin will control the orientation of the integrated cross bar mux.

After the RESETDB deassertion followed by internally generated reset signal and 1ms delay, the CROSS pin is

sampled and latched.

The system must make sure that CROSS meets t_su_CROSS and t_hd_CROSS with respect to power supply ramp

and RESETB deassertion per Power Supply Recommendations.

Changes to the state of the CROSS input while RESETB is high are ignored.

TUSB2E221

SNLS757B – JUNE 2024 – REVISED NOVEMBER 2024

www.ti.com

Submit Document Feedback

Product Folder Links: TUSB2E221

TUSB2E221 Datasheet(PDF) 26 Page - Texas Instruments

TUSB2E221 Datasheet(HTML) 26 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65

Datasheet Download

Link URL