| Electronic Components Datasheet Search |
|
CP2201 Datasheet(PDF) 51 Page - Silicon Laboratories |
|
|
|||||||||||||||||||||||||||||
CP2201 Datasheet(HTML) 51 Page - Silicon Laboratories |
|
51 / 108 page ![]() CP2200/1 Rev. 1.0 51 Register 18. TXCN: Transmit Control Register Register 19. TXBUSY: Transmit Busy Indicator Bit 7: OVRRIDE: Default Override 0: Settings for bits 5, 4, 3, 2, and 1 in TXCN will be ignored. MAC settings will take effect. 1: Settings for bits 5, 4, 3, 2, and 1 in TXCN will be applied. MAC settings will be overridden. Bit 6: UNUSED. Read = 0b, Write = don’t care. Bit 5: CRCENOV: CRC Enable 0: Disable CRC append on transmission. 1: Enable CRC append on transmission. Bit 4: PADENOV: Pad Enable 0: Disable padding of short frames. 1: Enable padding of short frames. Bit 3: TXPPKT: Transmit a PAUSE control packet 0: Normal packet transmission. Packet data will be obtained from the transmit buffer. 1: A PAUSE control packet with the value of TXPAUSEH:TXPAUSEL will be transmitted. Data in the transmit buffer will not be accessed. PAUSE control packets are only valid in full-duplex mode. Bit 2: BCKPRES: Apply Back Pressure 0: Normal packet transmission. Back pressure will not be applied. 1: Back pressure will be applied on transmission (only valid in half duplex mode). Bit 1: FDPLXOV: Full Duplex Operation Note: The transmit interface, MAC, and physical layer must be configured to the same duplex mode. 0: Transmit interface operates in half duplex mode. 1: Transmit interface operates in full duplex mode. Bit 0: TXGO: Transmit Packet Set this bit to ‘1’ to begin transmission of a packet. Note: TXGO should not be set to one if both TXSTART and TXEND are zero (i.e., no data has been added to the buffer). R/W R/W R/W R/W R/W R/W R/W W Reset Value OVRRIDE — CRCENOV PADENOV TXPPKT BCKPRES FDPLXOV TXGO 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x53 Bits 7–1: UNUSED. Read = 0000000b, Write = don’t care. Bit 0: TXBUSY: Packet Transmit Status 0: Packet Transmit is not in progress. 1: Packet Transmit is in progress. R R R RRR RR Reset Value — — — — — — — TXBUSY 00000000 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address: 0x54 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |