CP2201 datasheet(42/108 Pages) SILABS

42 / 108 page

CP2200/1

Rev. 1.0

9.7. De-Selecting Interrupt Sources

The power-fail (VDD Monitor) reset is automatically enabled after every power-on reset. The software reset is

enabled after every device reset, regardless of the reset source. The RSTEN register can be used to prevent either

of these two reset sources from generating a device reset.

Table 13. Reset Electrical Characteristics

VDD = 3.1 to 3.6 V, –40 to +85 °C unless otherwise specified.

Parameters

Conditions

Min

Typ

Max

UNITS

RST Output Low Voltage

IOL = 8.5 mA

—

0.6

RST Input High Voltage

0.7 x VDD

——

RST Input Low Voltage

—

0.3 x VDD

RST Input Pullup Current

—

µA

VDD POR Threshold (VRST)

2.2

2.4

2.6

Minimum /RST Low Time to

Generate a System Reset

—

µs

VDD Monitor Turn-on Time

100

—

µs

VDD Monitor Supply Current

—

Bits 7–3: UNUSED. Read = 00000b, Write = don’t care.

Bit 2:

ESWRST: Enable Software Reset

0: Software reset is not selected as a reset source.

1: Software reset is selected as a reset source.

Bit 1:

EPFRST: Enable Power Fail Reset

0: The power fail detection circuitry (VDD Monitor) is not selected as a reset source.

1: The power fail detection circuitry (VDD Monitor) is selected as a reset source.

Bit 0:

UNUSED. Read = 0b, Write = don’t care.

R/W

Reset Value

—

ESWRST EPFRST

—

00000100

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

Address:

0x72

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