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CP2201 Datasheet(PDF) 38 Page - Silicon Laboratories |
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CP2201 Datasheet(HTML) 38 Page - Silicon Laboratories |
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38 / 108 page ![]() CP2200/1 38 Rev. 1.0 9.1. Power-On Reset During power-up, the CP2200/1 is held in the reset state, and the /RST pin is driven low until VDD settles above VRST. A delay (TPORDelay) occurs between the time VDD reaches VRST and the time the device is released from reset; the typical delay is 5 ms. Refer to Table 13 for the Electrical Characteristics of the power supply monitor circuit. Figure 14. Reset Timing Power-On Reset VDD Monitor Reset /RST t 1.0 Logic HIGH Logic LOW TPORDelay VRST VDD |
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