HT46R652 datasheet(10/47 Pages) HOLTEK

10 / 47 page

HT46R652

Rev. 1.00

December 19, 2006

Stack Register

- STACK

The stack register is a special part of the memory used

to save the contents of the program counter. The stack

is organized into 16 levels and is neither part of the data

nor part of the program, and is neither readable nor

writeable. Its activated level is indexed by a stack

pointer, SP, which is neither readable nor writeable. At

the start of a subroutine call or an interrupt acknowledg-

ment, the contents of the program counter is pushed

onto the stack. At the end of the subroutine or interrupt

routine, signaled by a return instruction, RET or RETI,

the contents of the program counter is restored to its

previous value from the stack. After a device reset, the

SP will point to the top of the stack.

If the stack is full and a non-masked interrupt takes

place, the interrupt request flag is recorded but the ac-

knowledgment is still inhibited. Once the SP is decre-

mented, by RET or RETI, the interrupt will be serviced.

This feature prevents a stack overflow, allowing the pro-

grammer to use the structure easily. Likewise, if the

stack is full, and a

²CALL² is subsequently executed, a

stack overflow occurs and the first entry is lost as only

the most recent sixteen return addresses are stored.

Data Memory

- RAM

The data memory has a structure of 431

´8 bits, and is

divided into two functional groups, namely the special

function registers, 47

´8 bits, and the general purpose

data memory, Bank0: 192

´8 bits and Bank2: 192´8 bits

most of which are readable/writeable, although some

are read only. The special function registers are over-

lapped in every bank.

Any unused remaining space before 40H is reserved for

future expanded usage and if read will return a

²00H²

value. The Data Memory space before 40H will overlap

in each bank.

The general purpose data memory, addressed from 40H

to FFH (Bank0; BP=0 or Bank2; BP=2), is used for data

and control information under instruction commands. All

of the data memory areas can handle arithmetic, logic,

increment, decrement and rotate operations directly.

Except for some dedicated bits, each bit in the data

memory can be set and reset by

²SET [m].i² and ²CLR

[m].i

². They are also indirectly accessible through mem-

ory pointer registers, MP0 and MP1.

After first setting up BP to the value of

²01H² or ²02H² to

access either bank 1 or bank 2 respectively, these banks

must then be accessed indirectly using the Memory

Pointer MP1. With BP set to a value of either

²01H² or

²02H², using MP1 to indirectly read or write to the data

memory areas with addresses from 40H~FFH, will re-

sult in operations to either bank 1 or bank 2. Directly ad-

dressing the Data Memory will always result in Bank 0

being accessed irrespective of the value of BP.

S p e c i a l P u r p o s e

D a t a M e m o r y

I n d i r e c t A d d r e s s i n g R e g i s t e r 0

M P 0

I n d i r e c t A d d r e s s i n g R e g i s t e r 1

M P 1

B P

A C C

P C L

T B L P

T B L H

R T C C

S T A T U S

I N T C 0

T M R 0 H

T M R 0 L

T M R 0 C

T M R 1 H

T M R 1 L

T M R 1 C

P A

P A C

P B

P B C

P C

P C C

P D

P D C

P W M 0

P W M 1

P W M 2

P W M 3

I N T C 1

P W M 4

P W M 5

P W M 6

P W M 7

A D R L

A D R H

A D C R

A C S R

P W M 8

P W M 9

P W M 1 0

P W M 1 1

P W M 1 2

P W M 1 3

P W M 1 4

P W M 1 5

: U n u s e d

R e a d a s " 0 0 "

G e n e r a l P u r p o s e

D a t a M e m o r y

( 3 8 4 B y t e s )

F F H

4 0 H

3 F H

0 0 H

0 1 H

0 2 H

0 3 H

0 4 H

0 5 H

0 6 H

0 7 H

0 8 H

0 9 H

0 A H

0 B H

0 C H

0 D H

0 E H

0 F H

1 0 H

1 1 H

1 2 H

1 3 H

1 4 H

1 5 H

1 6 H

1 7 H

1 8 H

1 9 H

1 A H

1 B H

1 C H

1 D H

1 E H

1 F H

2 0 H

2 1 H

2 2 H

2 3 H

2 4 H

2 5 H

2 6 H

2 7 H

2 8 H

2 9 H

2 A H

2 B H

2 C H

2 D H

2 E H

2 F H

RAM Mapping

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