HT46R652 datasheet(23/47 Pages) HOLTEK

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HT46R652

Rev. 1.00

December 19, 2006

Parameter

AC (0~1)

Duty Cycle

Modulation cycle i

(i=0~1)

i<AC

DC + 1

128

³AC

128

The modulation frequency, cycle frequency and cycle

duty of the PWM output signal are summarised in the

following table.

PWM

Modulation Frequency

PWM Cycle

Frequency

PWM Cycle

Duty

fSYS/64 for (6+2) bits mode

fSYS/128 for (7+1) bits mode

fSYS/256

[PWM]/256

A/D Converter

An 8-channel, 12-bit resolution A/D converter is imple-

mented within the microcontroller. The reference volt-

age is VDD. The A/D converter contains 4 special

registers which are; ADRL, ADRH, ADCR and ACSR.

The ADRH and ADRL registers contain the A/D result

sion values and are read-only. After the A/D conversion

is completed, the ADRH and ADRL should be read to

get the conversion result data. The ADCR is an A/D con-

verter control register, which defines the A/D channel

number, analog channel select, start A/D conversion

control bit and the end of A/D conversion flag. This reg-

ister is used to start an A/D conversion, define the PB

configuration, select the analog channel, and give the

START bit a rising and falling edge (0

®1®0). At the end

of the A/D conversion, the EOCB bit will be automati-

cally cleared to indicate that the conversion process has

finished. The ACSR is the A/D clock setting register,

which is used to select the A/D clock source.

The A/D converter control register is used to control the

A/D converter. Bits 2~0 of ADCR are used to select the

analog input channel. There are a total of eight selectable

channels. Bits 5~3 of ADCR are used to set the PB con-

figurations. PB can be setup to be either an analog input

or digital I/O line decided by these 3 bits. Once a PB line

is selected as an analog input, the I/O function and

pull-high resistor of the I/O line is disabled and the A/D

converter circuit is powered-on. The EOCB bit, bit6 of

ADCR, is the end of A/D conversion flag. This bit can be

monitored to know when the A/D conversion has fin-

ished. The START bit in the ADCR register is used to initi-

ate an A/D conversion process. By providing the START

bit with a rising edge and then a falling edge, the A/D

conversion process will be initiated. In order to ensure

that the A/D conversion has completed, the START bit

should remain at

²0² until the EOCB has cleared to ²0²,

which indicates the end of A/D conversion.

Bit 7 of the ACSR register is used for test purposes only

and must not be used for other purposes by the applica-

tion program. Bit1 and bit0 of the ACSR register are

used to select the A/D clock source.

When the A/D conversion has completed, the A/D inter-

rupt request flag will be set. The EOCB bit will be set to

²1² when the START bit is set from ²0² to ²1².

Important Note for A/D initialisation:

Special care must be taken to initialise the A/D con-

verter each time the Port B A/D channel selection bits

are modified, otherwise the EOCB flag may be in an un-

defined condition. An A/D initialisation is implemented

by setting the START bit high and then clearing it to zero

within 10 instruction cycles of the Port B channel selec-

tion bits being modified. Note that if the Port B channel

selection bits are all cleared to zero then an A/D initialis-

ation is not required.

Bit No.

Label

Function

ADCS0

ADCS1

Selects the A/D converter clock source

00= system clock/2

01= system clock/8

10= system clock/32

11= undefined

2~7

Unused bit, read as

²0²

ACSR (27H) Register

HT46R652 Datasheet(PDF) 23 Page - Holtek Semiconductor Inc

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