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HT46R652 Datasheet(PDF) 14 Page - Holtek Semiconductor Inc

Part # HT46R652
Description  A/D with LCD Type 8-Bit OTP MCU
PDF  47 Pages
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Manufacturer  HOLTEK [Holtek Semiconductor Inc]
Direct Link  http://www.holtek.com
Logo HOLTEK - Holtek Semiconductor Inc

HT46R652 Datasheet(HTML) 14 Page - Holtek Semiconductor Inc

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HT46R652
Rev. 1.00
14
December 19, 2006
Watchdog Timer
- WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or an instruction clock
(system clock/4) or a real time clock oscillator (RTC os-
cillator). The timer is designed to prevent a software
malfunction or sequence from jumping to an unknown
location with unpredictable results. The WDT can be
disabled by options. But if the WDT is disabled, all exe-
cutions related to the WDT lead to no operation.
If the internal WDT oscillator, which is an RC oscillator
with a nominal period of 65
ms at 5V, is selected, it is di-
vided by 2
12~215 , the actual ratio chosen by configura-
tion option, to get the WDT time-out period. The
minimum period for the WDT time-out period is about
300ms~600ms. This time-out period may vary with tem-
perature, VDD and process variations. By selection the
WDT configuration option, longer time-out periods can
be realised. If the WDT time-out is selected as 2
15, the
maximum time-out period is divided by 2
15~216 about
2.1s~4.3s. If the WDT oscillator is disabled, the WDT
clock may still come from the instruction clock and oper-
ate in the same manner except that in the Power Down
mode the WDT will stop counting and lose its protecting
function. If the device operates in a noisy environment,
using the WDT internal RC oscillator is strongly recom-
mended, since the HALT instruction will stop the system
clock.
The WDT overflow under normal operation initiates a de-
vice reset which sets the status bit
²TO². In the Power
Down mode, the overflow initiates a warm reset, in which
only the Program Counter and Stack Pointer are reset to
zero. To clear the contents of the WDT, there are three
methods that can be adopted. These are, an external re-
set, which is a low level on the RES pin, a software in-
struction and a
²HALT² instruction. There are two types of
software instructions; a single
²CLR WDT² instruction or
the pair of instructions,
²CLR WDT1² and ²CLR WDT2².
Of these two types of instruction, only one type of instruc-
tion can be active at a time depending on a configuration
option
-²CLR WDT² times selection option. If the ²CLR
WDT
² is selected (i.e., CLR WDT times equal one), any
execution of the
²CLR WDT² instruction clears the WDT.
In the case where the two
²CLR WDT1² and ²CLR
WDT2
² instruction are chosen (i.e., CLR WDT times
equal two), these two instructions have to be executed to
clear the WDT; otherwise, the WDT may reset the chip
due to a time-out.
Multi-function Timer
The device provides a multi-function timer for the WDT,
time base and RTC but with different time-out periods.
The multi-function timer consists of an 8-stage divider
and a 7-bit prescaler, with the clock source coming from
the WDT OSC, the RTC OSC or the instruction clock,
which is the system clock divided by 4. The multi-func-
tion timer also provides a selectable frequency signal,
whose division ratio ranges from fS/2
2 to f
S/2
8, for LCD
driver circuits, and a selectable frequency signal, rang-
ing from fS/2
2 to f
S/2
9, for the buzzer output selectable via
configuration options.
It is recommended to select a frequency as close as
possible to 4kHz for the LCD driver circuits to obtain the
best display clarity.
Time Base
The time base offers a periodic time-out period to gener-
ate a regular internal interrupt. Its time-out period
ranges from 2
12/f
S to 2
15/f
S selected by a configuration
option. If a time base time-out occurs, the related inter-
rupt request flag, TBF; bit 5 of INTC1, will be set. If the
interrupt is enabled, and the stack is not full, a subrou-
tine call to location 14H occurs.
S y s t e m C l o c k / 4
D i v i d e r
R O M
C o d e
O p t i o n
W D T
O S C
1 2 k H z
R T C
O S C 3 2 7 6 8 H z
T
R
T
R
f S
f S / 2 8
T i m e - o u t R e s e t
2 1 5 / f S ~ 2 1 6 / f S
2 1 4 / f S ~ 2 1 5 / f S
2 1 3 / f S ~ 2 1 4 / f S
2 1 2 / f S ~ 2 1 3 / f S
W D T
P r e s c a l e r
M a s k O p t i o n
W D T C l e a r
C K
C K
Watchdog Timer
f s
D i v i d e r
P r e s c a l e r
R O M C o d e O p t i o n
L C D D r i v e r ( f S / 2 2 ~ f S / 2 8 )
B u z z e r ( f S / 2 2 ~ f S / 2 9 )
T i m e B a s e I n t e r r u p t
2 1 2 / f S ~ 2 1 5 / f S
R O M
C o d e
O p t i o n
Time Base



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