HT49CV3 datasheet(17/44 Pages) HOLTEK

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HT49RV3/HT49CV3

Rev. 1.30

March 20, 2007

original level and resets the TON. The measured result

remains in the timer/event counter even if the activated

transient occurs again. In other words, only 1-cycle

measurement can be made until the TON bit is set. The

cycle measurement will continue as long as it receives

further transient pulse. In this operation mode, the

timer/event counter begins counting not according to

the logic level but to the transient edges. In the case of

counter overflows, the counter is reloaded from the

timer/event counter register and issues an interrupt re-

quest, as in the other two modes, i.e., the event and

timer modes.

To enable the counting operation, the Timer ON bit

(TON; bit 4 of the TMR0C or TMR1C) should be set to 1.

In the pulse width measurement mode, TON is automat-

ically cleared after the measurement cycle is completed.

But in the other two modes, TON can only be reset by in-

structions. The overflow of the Timer/Event Counter 0/1

is one of the wake-up sources and can also be applied

to a PFD (Programmable Frequency Divider) output at

PA3 by options. Only one PFD (PFD0 or PFD1) can be

applied to PA3 by options. No matter what the operation

mode is, writinga0to ET0I or ET1I disables the related

interrupt service. When the PFD function is selected, ex-

ecuting

²SET [PA].3² instruction will enable the PFD out-

put and executing

²CLR [PA].3² instruction will disable

the PFD output.

In the case of timer/event counter OFF condition, writing

data to the timer/event counter preload register also re-

loads that data to the timer/event counter. But if the

timer/event counter is turned on, data written to the

timer/event counter is kept only in the timer/event coun-

ter preload register. The timer/event counter still contin-

ues its operation until an overflow occurs.

When the timer/event counter (reading TMR0/TMR1) is

read, the clock is blocked to avoid errors, as this may re-

sults in a counting error. Blocking of the clock should be

taken into account by the programmer. It is strongly rec-

ommended to load the desired value into the

TMR0/TMR1 register first, before turning on the related

timer/event counter, for proper operation since the initial

value of the TMR0/TMR1 is unknown. Due to the

timer/event counter scheme, the programmer should

pay special attention on the instruction to enable then

disable the timer for the first time, whenever there is a

need to use the timer/event counter function, to avoid

unpredictable result. After this procedure, the

timer/event function can be operated normally.

Bits 2~0 of the TMR0C can be used to define the pre-

scaling stages of the internal clock sources of the timer/

event counter. The definitions are as shown. The over-

flow signal of the timer/event counter can be used to

generate the PFD signal.

R e l o a d

O v e r f l o w

t o I n t e r r u p t

P F D 0

P A 3 D a t a C T R L

T 0 M 1

T 0 M 0

T M R 0

T 0 E

T 0 M 1

T 0 M 0

T 0 O N

P u l s e W i d t h

M e a s u r e m e n t

M o d e C o n t r o l

1 6 - b i t T i m e r / E v e n t C o u n t e r

P r e l o a d R e g i s t e r

1 6 - b i t T i m e r / E v e n t C o u n t e r

( T M R 0 H / T M R 0 L )

D a t a B u s

8 - s t a g e P r e s c a l e r

8 - 1 M U X

f S Y S

f I N T

T 0 P S C 2 ~ T 0 P S C 0

Timer/Event Counter 0

R e l o a d

O v e r f l o w

t o I n t e r r u p t

P F D 1

P A 3 D a t a C T R L

T 1 M 1

T 1 M 0

T M R 1

T 1 E

T 1 M 1

T 1 M 0

T 1 O N

P u l s e W i d t h

M e a s u r e m e n t

M o d e C o n t r o l

1 6 - b i t T i m e r / E v e n t C o u n t e r

P r e l o a d R e g i s t e r

1 6 - b i t T i m e r / E v e n t C o u n t e r

( T M R 1 H / T M R 1 L )

D a t a B u s

f I N T

f S Y S / 4

3 2 7 6 8 H z

T 1 S

Timer/Event Counter 1

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