HT49CV3 datasheet(22/44 Pages) HOLTEK

22 / 44 page

HT49RV3/HT49CV3

Rev. 1.30

March 20, 2007

¨ Slave mode operation

Step1: CKS don

¢t care and select M1, M0 =11

Step2: Select CSEN, MLS (the same as the master)

Step3: Set SBEN

Step4: Writing data to SBDR

- data is stored in the TXRX buffer

- waiting for master clock signal (and SCS): SCK

- go to step 5

Note: SIO internal operation:

* SCK (SCS) received

* output data in TXRX buffer and SDI data

is shifted into TXRX buffer

* data transferred, data in TXRX buffer is

latched into SBDR

Step5: Check WCOL

- WCOL=1, clear WCOL, go to step 4

- WCOL=0, go to step 6

Step6: Check TRFor waiting for serial bus interrupt

Step7: Read data from SBDR

Step8: Clear TRF

Step9: Go to step 4

Input/Output Ports

There are 17 bidirectional input/output lines in the

microcontroller, labeled as PA, PB, PC and PD, which

are mapped to the data memory of [12H], [14H], [16H]

and [18H], respectively. All of these I/O ports can be

used for input and output operations. For input opera-

tion, these ports are non-latching, that is, the inputs

must be ready at the T2 rising edge of instruction

²MOV

A,[m]

² (m=12H, 14H, 16H or 18H). For output operation,

all the data is latched and remains unchanged until the

output latch is rewritten.

Each I/O line has its own control register (PAC, PBC,

PCC, PDC) to control the input/output configuration.

With this control register, CMOS output or Schmitt Trig-

ger input with or without pull-high resistor structures can

be reconfigured dynamically under software control. To

function as an input, the corresponding latch of the con-

trol register must write a

²1². The input source also de-

pends on the control register. If the control register bit is

²1², the input will read the pad state. If the control regis-

ter bit is

²0², the contents of the latches will move to the

internal bus. The latter is possible in the

²read-modify-

write

² instruction.

For an output function, CMOS is the only configuration.

These control registers are mapped to locations 13H,

15H, 17H and 19H.

After a chip reset, these input/output lines remain at high

levels or floating state (depending on pull-high options).

Each bit of these input/output latches can be set or

cleared by

²SET [m].i² and ²CLR [m].i² (m=12H, 14H,

16H or 18H) instructions.

Some instructions first input data and then follow the

output operations. For example,

²SET [m].i², ²CLR

[m].i

², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of port A has the capability of waking-up the

device.

Each I/O port has a pull-high option. Once the pull-high

option is selected, the I/O port has a pull-high resistor,

otherwise, there

¢s none. Take note that a non-pull-high

I/O port operating in input mode will cause a floating

state.

The PA3 pin is pin-shared with the PFD signal. If the

PFD option is selected, the output signal in the output

mode of PA3 will be the PFD signal generated by the

timer/event counter overflow signal. The input mode al-

ways retains its original functions. Once the PFD option

is selected, the PFD output signal is controlled by the

PA3 data register only. Writing a

²1² to the PA3 data reg-

ister will enable the PFD output function and writing a

²0² will force the PA3 pin to remain at ²0². The I/O func-

tions of PA3 are shown below.

I/O

Mode

I/P

(Normal)

O/P

(Normal)

I/P

(PFD)

O/P

(PFD)

PA3

Logical

Input

Logical

Output

Logical

Input

PFD

(Timer on)

Note: The PFD frequency is the timer/event counter

overflow frequency divided by 2.

The descriptions of PFD control signal and PFD output

frequency are listed in the following table.

Timer

Preload

Value

PA3 Data

PA3 Pad

State

PFD

Frequency

OFF

PFD

fTMR/[2

´(M-N)]

Note:

²X² stands for unused

²U² stands for unknown

²M² is ²65536² for PFD0 or PFD1

²N² is preload value for timer/event counter

²fTMR² is input clock frequency for timer/event

counter

The PA0 and PA1 pins are pin-shared with the BZ and

BZ signal, respectively. If the BZ/BZ option is selected,

the output signal in the output mode of PA0/PA1 will be

the buzzer signal generated by the multi-function timer.

The input mode always remains in its original function.

Once the BZ/BZ option is selected, the buzzer output

signal are controlled by the PA0/PA1 data register only.

HT49CV3 Datasheet(PDF) 22 Page - Holtek Semiconductor Inc

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