MSC8122 datasheet(34/88 Pages) FREESCALE

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MSC8122 Technical Data, Rev. 13

1-24

Freescale Semiconductor

Signals/Connections

1.8 EOnCE Event and JTAG Test Access Port Signals

The MSC8122 uses two sets of debugging signals for the two types of internal debugging modules: EOnCE and the

JTAG TAP controller. Each internal SC140 core has an EOnce module, but they are all accessed externally by the

same two signals EE0 and EE1. The MSC8122 supports the standard set of test access port (TAP) signals defined by

IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture specification and described in Table 1-9.

1.9 Reserved Signals

ETHCRS

ETHRXD

Input

Carrier Sense

In MII mode, indicates that either the transmit or receive medium is non-idle.

Ethernet Receive Data

In SMII mode, used for the Ethernet receive data.

Table 1-9.

JTAG TAP Signals

Signal Name

Type

Signal Description

EE0

Input

EOnCE Event Bit 0

Puts the internal SC140 cores into Debug mode.

EE1

Output

EOnCE Event Bit 1

Indicates that at least one on-device SC140 core is in Debug mode.

TCK

Input

Test Clock—Synchronizes JTAG test logic.

TDI

Input

Test Data Input—A test data serial signal for test instructions and data. TDI is sampled on the rising edge

of TCK and has an internal pull-up resistor.

TDO

Output

Test Data Output—A test data serial signal for test instructions and data. TDO can be tri-stated. The

signal is actively driven in the shift-IR and shift-DR controller states and changes on the falling edge of

TCK.

TMS

Input

Test Mode Select—Sequences the test controller state machine, is sampled on the rising edge of TCK,

and has an internal pull-up resistor.

TRST

Input

Test Reset—Asynchronously initializes the test controller; must be asserted during power up.

Table 1-10.

Reserved Signals

Signal Name

Type

Signal Description

TEST

Input

Test

For manufacturing testing. You must connect this pin to GND.

Table 1-8.

Dedicated Ethernet Signals

Signal Name

Type

Signal Description

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