AS8267 datasheet(116/136 Pages) AMSCO

116 / 136 page

Data Sheet AS8267 / AS8268

Revision 1.0, 19-Jun-07

Page 116 of 136

Enable Signals Register

The enable signals register includes power-down signals and other control signals.

MSB

LSB

sel_spi2

enable_crc

u2clkoff

u1clkoff

dam

sdmi2_pd

afe_pd

Bit

Symbol

Function

Not used

sel_spi2

Selects the SPI path

0: selects path to SPI_Flash (slave mode)

1: selects path to SPI2 (master mode)

enable_crc Enables checksum functionality during read/write accesses to XDATA address space or

EEPROM. If enabled, a 16-bit checksum word (see Note below) is sent after the data, which is

checked by the SCT (in case of ‘write’) or can be checked by an external component (in case of

‘read’).

0: checksum disabled

1: checksum enabled

u2clkoff

Switches off the UART2 clock (which is also running at the highest system frequency ‘mclk’):

0: clock active

1: clock switched off

u1clkoff

Switches off the UART1 clock (which is running at the highest system frequency ‘mclk’):

0: clock active

1: clock switched off

dam

Select direct access mode for UART1; in case of ‘dam’ input data will no longer be interpreted as

commands.

0: direct access mode off 1: dam on

sdmi2_pd

Set power-down for current channel 2 (active high)

0: no power-down

1: I2 powered down

afe_pd

Set power-down for the entire analog front end (AFE)

0: AFE powered up

1: AFE powered down

Note: The checksum is calculated using the following formula:

g(x) = x

16 + x12 + x5 + 1

In dam mode no interrupt will be triggered, therefore the SCON register has to be polled.

MCUCLKDIV Register (‘mcu_clk’)

The MCU clock divider (mcuclkdiv) divides down the main clock (Mclk) which is the output from the low power

oscillator.

Division of the mcu_clk frequency is provided to enable low power operating modes, for example when the

AS8267 / AS8268 ICs are in a battery operating mode, when VDDD is connected to a battery.

MSB

LSB

mcuclkdiv.2

mcuclkdiv.1

mcuclkdiv.0

Bit

Symbol

Function

Not used

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