PIC16F84AT-20SLASHSSROM datasheet(32/88 Pages) MICROCHIP

32 / 88 page

PIC16F84A

DS35007B-page 30

6.9

Context Saving During Interrupts

During an interrupt, only the return PC value is saved

on the stack. Typically, users wish to save key register

values during an interrupt (e.g., W register and

STATUS register). This is implemented in software.

The code in Example 6-1 stores and restores the

STATUS and W register’s values. The user defined

registers, W_TEMP and STATUS_TEMP are the tem-

porary storage locations for the W and STATUS

registers values.

Example 6-1 does the following:

Stores the W register.

Stores the STATUS register in STATUS_TEMP.

Executes the Interrupt Service Routine code.

Restores the STATUS (and bank select bit)

Restores the W register.

EXAMPLE 6-1:

SAVING STATUS AND W REGISTERS IN RAM

6.10

Watchdog Timer (WDT)

The Watchdog Timer is a free running On-Chip RC

Oscillator which does not require any external

components. This RC oscillator is separate from the

RC oscillator of the OSC1/CLKIN pin. That means that

the WDT will run even if the clock on the OSC1/CLKIN

and OSC2/CLKOUT pins of the device has been

stopped, for example, by execution of a SLEEP

instruction. During normal operation, a WDT time-out

generates a device RESET. If the device is in SLEEP

mode, a WDT wake-up causes the device to wake-up

and continue with normal operation. The WDT can be

permanently disabled by programming configuration bit

WDTE as a '0' (Section 6.1).

6.10.1

WDT PERIOD

The WDT has a nominal time-out period of 18 ms, (with

prescaler).

The

time-out

periods

vary

with

temperature, VDD and process variations from part to

part (see DC specs). If longer time-out periods are

desired, a prescaler with a division ratio of up to 1:128

can be assigned to the WDT under software control by

writing to the OPTION_REG register. Thus, time-out

periods up to 2.3 seconds can be realized.

The CLRWDT and SLEEP instructions clear the WDT

and the postscaler (if assigned to the WDT) and pre-

vent it from timing out and generating a device

RESET condition.

The TO bit in the STATUS register will be cleared upon

a WDT time-out.

PUSH

MOVWF

W_TEMP

; Copy W to TEMP register,

SWAPF

STATUS,

; Swap status to be saved into W

MOVWF

STATUS_TEMP

; Save status to STATUS_TEMP register

ISR

; Interrupt Service Routine

; should configure Bank as required

POP

SWAPF

STATUS_TEMP,W

; Swap nibbles in STATUS_TEMP register

; and place result into W

MOVWF

STATUS

; Move W into STATUS register

; (sets bank to original state)

SWAPF

W_TEMP,

; Swap nibbles in W_TEMP and place result in W_TEMP

SWAPF

W_TEMP,

; Swap nibbles in W_TEMP and place result into W

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