PIC16F84AT-20SLASHSSROM datasheet(7/88 Pages) MICROCHIP

7 / 88 page

DS35007B-page 5

PIC16F84A

2.0

MEMORY ORGANIZATION

There are two memory blocks in the PIC16F84A.

These are the program memory and the data memory.

Each block has its own bus, so that access to each

block can occur during the same oscillator cycle.

The data memory can further be broken down into the

general purpose RAM and the Special Function

Registers (SFRs). The operation of the SFRs that

control the “core” are described here. The SFRs used

to control the peripheral modules are described in the

section discussing each individual peripheral module.

The data memory area also contains the data

EEPROM memory. This memory is not directly mapped

into the data memory, but is indirectly mapped. That is,

an indirect address pointer specifies the address of the

data EEPROM memory to read/write. The 64 bytes of

data EEPROM memory have the address range

0h-3Fh. More details on the EEPROM memory can be

found in Section 3.0.

Additional information on device memory may be found

in the PICmicro™ Mid-Range Reference Manual,

(DS33023).

2.1

Program Memory Organization

The PIC16FXX has a 13-bit program counter capable

of addressing an 8K x 14 program memory space. For

the PIC16F84A, the first 1K x 14 (0000h-03FFh) are

physically implemented (Figure 2-1). Accessing a loca-

tion above the physically implemented address will

cause a wraparound. For example, for locations 20h,

420h, 820h, C20h, 1020h, 1420h, 1820h, and 1C20h,

the instruction will be the same.

The RESET vector is at 0000h and the interrupt vector

is at 0004h.

FIGURE 2-1:

PROGRAM MEMORY MAP

AND STACK - PIC16F84A

PC<12:0>

Stack Level 1

•

Stack Level 8

RESET Vector

Peripheral Interrupt Vector

•

CALL, RETURN

RETFIE, RETLW

0000h

0004h

1FFFh

3FFh

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