TMPR4938 datasheet(105/716 Pages) TOSHIBA

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Chapter 6 Clocks

6-1

Clocks

6.1

TX4938 Clock Signals

Figure 6.1.1 shows the configuration of TX4938 blocks and clock signals. Table 6.1.1 describes each clock

signal. Table 6.1.2 shows the relationship among different clock signals when the CPU clock frequency is

266 MHz. Table 6.1.3 shows the relationship among different clock signals when the CPU clock frequency is

300 MHz. Table 6.1.4 shows the relationship among different clock signals when the CPU clock frequency is

333 MHz.

Figure 6.1.1 TX4938 Block and Clock Configuration

SDRAMC

PCIC

TX49/H3 core

IRC

EBUSC

DMAC

CPUCLK

GBUSCLK

IMBUSCLK

MASTERCLK

SYSCLK

SDCLK[3:0]

SDCLKIN

PCICLK[5:0]

PCICLKIN

TX4938

Data input latch

CLKGATE

PCICLKO

×1

TCLK

1/2

ADDR[3][1:0]

PLL1

ADDR[11:10]

(CCFG.

PCIDIVMODE

ADDR[14:13]

PCI device

External

device

PLL2

Oscillato

×1

1/1

1/2

1/3

1/4

DMACKD

PCICKD

PIOCKD

TM2CKD

TM1CKD

TM0CKD

SIO1CKD

PIO

CLKGATE

TMR2

TMR1

TMR0

SIO1

SIO0

SDRAM

SCLK

ACLC

BITCLK

×4

EJTAG/DSU

DCLK

TCK

ADDR[2]

1/4

1/4.5

1/5

1/5.5

1/8

1/9

1/10

1/11

×2

×2.5

×3

×4

x4.5

NDFMC

SRAMC

NDFCKD

SRAMCKD

1/2

1/4

PCIC1

ETHERC1

ETHERC0

ADDR[16]

ETH0CKD

PCIC1CKD

ETH1CKD

SPI

SIO0CKD

ACLCKD

SPICKD

SPICLK

E1RXCL

E1TXCL

E0RXCL

E0TXCL

CLKCTR

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