TMPR4938 datasheet(109/716 Pages) TOSHIBA

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Chapter 6 Clocks

6-5

Table 6.1.4 Relationship Among Different Clock Frequencies (for TMPR4938XBG-333, CPUCLK = 333 MHz)

Master Clock (Input)

and Boot Configured

Settings

Internal Clock

External Clock (Output)

SYSCLK (MHz)

PCICLK[5:0] (MHz) †

Boot Configured Settings

PCIDIVMODE[2:0]

CCFG Settings

PCIDIVMODE[2:0]

MASTERCLK

(MHz)

Boot

Configured

Setting

ADDR[3:0]

CPUCLK

(MHz)

GBUSCLK

(MHz)

IMBUSCLK

(MHz)

SDCLK

[3:0]

(MHz)

(1/1)

(1/2)

(1/3)

(1/4)

LLH

(1/4)

LHH

(1/4.5)

HLH

(1/5)

HHH

(1/5.5)

LLL

(1/8)

LHL

(1/9)

HLL

(1/10)

HHL

(1/11)

HHHH(x2.0)

HLHH(x8.0)

133

HHHL (x2.5)

HLHL (x10.0)

133

111

HHLH (x3.0)

HLLH (x12.0)

111

HHLL (x4.0)

HLLL (x16.0)

LHHH(x4.5)

LLHH (x18.0)

333

† The CCFG.PCIDIVMODE[2:1] field is setting by the boot configuration ADDR[11:10].

6.2

Power-Down Mode

6.2.1

Halt Mode and Doze Mode

The WAIT instruction causes the TX49/H3 core to enter either of the two low-power modes: Halt and

Doze. The TX49/H3 can exit from Halt or Doze mode upon an interrupt exception. Ensure, therefore,

that the TX49/H3 does not enter Halt or Doze mode when all interrupts are masked in the interrupt

controller.

The HALT bit of the TX49/H3 core Config register is used to select Halt or Doze mode. As the

TX4938 does not use the snoop function of the TX49/H3 core, the bit should be set to select Halt mode,

which achieves greater power reduction than Doze mode.

6.2.2

Power Reduction for Peripheral Modules

When the system does not use the DMA controller, PCI controller, serial I/O controller,

timers/counters, parallel I/O controller, or AC-link controller, it can stop the input clock for that module

to reduce power dissipation.

The clock control register (CLKCTR) is used to control whether to turn each clock on or off. The

module should be reset before its clock can be turned on or off. This reset is performed using the reset

bit for the specific module, provided in the clock control register. The reset also initializes the registers

of the module, thus requiring subsequent setup of necessary register values and other configurations.

Refer to Section 5.2.5, "Clock Control Register" for detail of the clock control register (CLKCTR).

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