TMPR4938 datasheet(207/716 Pages) TOSHIBA

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Chapter 8 DMA Controller

8-33

8.4.4

DMA Source Address Register (DM0SARn, DM1SARn)

Offset Address: DMAC0 0xB008 (ch. 0) / 0xB048 (ch. 1) / 0xB088 (ch. 2) / 0xB0C8 (ch. 3)

DMAC1 0xB808 (ch. 0) / 0xB848 (ch. 1) / 0xB888 (ch. 2) / 0xB8C8 (ch. 3)

Reserved

: Type

: Initial value

Reserved

SADDR[35:32]

R/W

: Type

⎯

: Initial value

SADDR[31:16]

R/W

: Type

⎯

: Initial value

SADDR[15:0]

R/W

: Type

⎯

: Initial value

Bits

Mnemonic

Field Name

Description

Read/Write

63:36

⎯

Reserved

⎯

35:0

SADDR

Source Address

Source Address (Default: Undefined)

This field sets the physical address of the transfer source during Dual

Address transfer. This field sets the physical address of memory access

during Single Address transfer. This field is used for either Memory-to-I/O

or I/O-to-Memory transfers.

Refer to “8.3.7.1 Channel Register Settings During Single Address

Transfer” and “8.3.8.1 Channel Register Settings During Dual Address

Transfer” for more information.

During Burst transfer, the value changes once for each bus operation only

by the size that was transferred. During Single transfer, the value only

changes by the value specified by the DMA Source Address Increment

R/W

Figure 8.4.4 DMA Source Address Register

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