TMPR4951B datasheet(5/256 Pages) TOSHIBA

5 / 256 page

Table of Contents

Handling Precautions

TMPR4951B

1. Introduction ............................................................................................................................................................ 1-1

1.1

Overview........................................................................................................................................................ 1-1

1.2

Notation used in this manual.......................................................................................................................... 1-1

1.2.1

Numerical notation ................................................................................................................................ 1-1

1.2.2

Data notation ......................................................................................................................................... 1-1

1.2.3

Signal notation....................................................................................................................................... 1-1

1.2.4

Register notation ................................................................................................................................... 1-1

2. Features

............................................................................................................................................................... 2-1

2.1

Block Diagram ............................................................................................................................................... 2-2

2.2

Pin Description............................................................................................................................................... 2-3

2.2.1

TX4951B pin out (100-pin LQFP) ........................................................................................................ 2-3

3. TX49/L3 Core’s Registers ...................................................................................................................................... 3-1

3.1

CPU Registers................................................................................................................................................ 3-1

3.2

CP0 Registers................................................................................................................................................. 3-2

3.2.1

Index register (Reg

#0)........................................................................................................................... 3-3

3.2.2

Random register (Reg

#1) ...................................................................................................................... 3-4

3.2.3

EntryLo0 register (Reg#2) and EntryLo1 register (Reg#3)................................................................... 3-5

3.2.4

Context register (Reg#4) ....................................................................................................................... 3-6

3.2.5

PageMask Register (Reg#5) .................................................................................................................. 3-7

3.2.6

Wired Register (Reg

#6)......................................................................................................................... 3-8

3.2.7

BadVAddr Register (Reg

#8).................................................................................................................. 3-9

3.2.8

Count Register (Reg

#9)....................................................................................................................... 3-10

3.2.9

EntryHi Register (Reg

#10).................................................................................................................. 3-11

3.2.10

Compare Register (Reg

#11) ................................................................................................................ 3-12

3.2.11

Status Register (Reg#12) ..................................................................................................................... 3-13

3.2.12

Cause Register (Reg#13)..................................................................................................................... 3-16

3.2.13

EPC Register (Reg#14) ....................................................................................................................... 3-17

3.2.14

PRId Register (Reg

#15) ...................................................................................................................... 3-18

3.2.15

Config Register (Reg

#16) ................................................................................................................... 3-19

3.2.16

LLAddr Register (Reg

#17).................................................................................................................. 3-21

3.2.17

XContext Register (Reg

#20) ............................................................................................................... 3-22

3.2.18

Debug Register (Reg

#23).................................................................................................................... 3-23

3.2.19

DEPC Register (Reg#24) .................................................................................................................... 3-25

3.2.20

TagLo Register (Reg#28) and TagHi Register (Reg#29)..................................................................... 3-26

3.2.21

ErrorEPC Register (Reg#30) ............................................................................................................... 3-27

3.2.22

DESAVE Register (Reg

#31) ............................................................................................................... 3-28

4. Memory Management System ................................................................................................................................ 4-1

4.1

Address Space Overview ............................................................................................................................... 4-1

4.1.1

Virtual Address Space ........................................................................................................................... 4-1

4.1.2

Physical Address Space ......................................................................................................................... 4-2

4.1.3

Virtual-to-Physical Address Translation ................................................................................................ 4-2

4.1.4

32-bit Mode Address Translation .......................................................................................................... 4-3

4.1.5

64-bit Mode Address Translation .......................................................................................................... 4-4

4.2

Operating Modes............................................................................................................................................ 4-5

4.2.1

User Mode Operations........................................................................................................................... 4-5

4.2.2

Supervisor Mode Operations................................................................................................................. 4-7

4.2.3

Kernel Mode Operations ....................................................................................................................... 4-9

4.3

Translation Lookaside Buffer....................................................................................................................... 4-16

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