ACT4921 datasheet(28/35 Pages) QORVO

28 / 35 page

Data Sheet Rev. B, January 2020 | Subject to change without notice

28 of 35

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ACT4921

Power Loss Protection with 6A eFuse

Table 9: Health Check Discharge Time

HMON_TSET[2:0]

HMON_TSET[3] (ms)

000

384

001

512

010

640

011

768

100

896

101

1024

110

128

1152

111

256

1280

PC BOARD LAYOUT GUIDANCE

Proper parts placement and PCB layout are critical to

the operation of switching power supplies. Follow the

following

layout

guidelines

when

designing

the

ACT4921 PCB. Refer to the Qorvo ACT4921 Evaluation

Kit for layout guidance.

Place the buck input capacitors as close as possible to

the IC. Connect the input capacitors directly between

STR and PGND pins on the top layer. Routing these

traces on the top layer eliminates the need for vias.

Minimize the switch node trace length between

the SW pin and the inductor. Optimal switch

node routing is to run the trace between the in-

put capacitor’s pads. Using 1206 or larger sized

input capacitors is recommended. Avoid routing

sensitive analog signals near these high fre-

quency, high dV/dt traces.

The Buck output capacitors should be placed

by the VOUT pin and connected directly to the

VOUT pin and ground plane with short and wide

traces. Note that the buck output capacitors do

not connect to the VB pin or inductor. The out-

put capacitor ground should make a short con-

nection to the input capacitor ground. If required,

use multiple vias.

The FB pin should be Kelvin connected to the

output capacitor through the shortest possible

route, while keeping sufficient distance from

switching node to prevent noise injection. The

IC regulates the output voltage to this Kelvin

connection.

Connect the PGND and AGND ground pins

must be electrically connected together. The

AGND ground plane should be isolated from

the rest of the PCB power ground.

Remember that all open drain outputs need

pull-up resistors.

Connect the exposed pad directly to the top

layer ground plane. Connect the top layer

ground plane to both internal ground planes

and the PCB backside ground plane with ther-

mal vias. Provide ground plane routing on mul-

tiple layers to allow the IC’s heat to flow into the

PCB and then spread radially from the IC. Avoid

cutting the ground planes or adding vias that re-

strict the radial flow of heat.

The following components should be con-

nected to the AGND plane.

SS cap

BSET resistor

ISET resistor

COMP resistor and capacitors

FB resistor

VINS resistor

The ACT4921 footprint should connect pins 31,

32, and 33 on the top layer. It should connect

pins 28 and 29 on the top layer. It should con-

nect pins 25, 26, 27, and 35 on the top layer. It

should connect pins 9 and 10 to the exposed

pad on the top layer. Refer to the evaluation kit

layout for

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