AD4080BBCZ datasheet(39/94 Pages) AD

39 / 94 page

Data Sheet

AD4080

DIGITAL INTERFACE

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Rev. A | 39 of 94

Table 16. Device Status Data Sent Through the SDO in Long Instruction Mode (SHORT_INSTRUCTION = 0) (Continued)

Bit

Name

Description

CRC_ERR

Interface Status A Register Bit 3: CRC Error. This bit is set when the SPI controller does not send a CRC value or when the CRC

value calculated by the device does not match the value received from the SPI controller.

WR_TO_RD_ONLY_REG_ERR Interface Status A Register Bit 2: Write to Read Only Register Error. Write to Read Only Register Attempted. This bit is set when

the user attempts a write to a register that is read-only.

REGISTER_PARTIAL_

ACCESS_ERR

Interface Status A Register Bit 1: Register Partial Access Error. This bit is set when a fewer than expected number of bytes are

read from or written to in a multibyte register access. This bit is only valid when strict register access is enabled.

ADDRESS_INVALID_ERR

Interface Status A Register Bit 0: Invalid Address Error. Attempt to read or write nonexistent register address. This bit is set when

the user tries to access register addresses outside the allowed memory map space.

Table 17. Device Status Data Sent Through the SDO in Short Instruction Mode (SHORT_INSTRUCTION = 1)

Bit

Name

Description

Not applicable

Bit 7 is always 0.

POR_FLAG

Device Status Register Bit 0: POR Status. Allows user to detect when a POR event has occurred. A POR is triggered at power-up

or when the logic supply drops to less than some threshold value or when the user issues a software reset.

0: POR Flag Cleared.

1: POR Event Detected.

NOT_READY_ERR

Interface Status A Register Bit 7: Device Not Ready For Transaction Error. This bit is set if the user attempts to execute an SPI

transaction before the completion of digital initialization.

CLOCK_COUNT_ERR

Interface Status A Register Bit 4: Clock Count Error. This bit is set when an incorrect number of clocks is detected in a transaction.

CRC_ERR

Interface Status A Register Bit 3: CRC Error. This bit is set when the SPI controller does not send a CRC, or when the CRC value

calculated by the device does not match the value sent by the SPI controller.

WR_TO_RD_ONLY_REG_ERR Interface Status A Register Bit 2: Write To Read-only Register Error. This bit is set when the user attempts a write to a register that

is read only.

REGISTER_PARTIAL_

ACCESS_ERR

Interface Status A Register Bit 1: Register Partial Access Error. This bit is set when a fewer than expected number of bytes are

read from or written to in a multibyte register access. This bit is only valid when strict register access is enabled.

ADDRESS_INVALID_ERR

Interface Status A Register Bit 0: Invalid Address Error. This bit is set when the user tries to read from or write to a register

address outside the allowed memory map space.

Configuration Cyclical Redundancy Check

(CRC)

The AD4080 includes optional configuration error detection based

on an 8-bit cyclical redundancy check algorithm. When enabled, an

8-bit checksum is inserted into the serial data output stream (SDO)

during the data phase after each complete register transaction. De-

pending on the register access type,that is, read or write, the host

is expected to conditionally provide a corresponding checksum to

the SDI immediately following each register access. The interface

controller uses the host supplied checksum to determine if a CRC

error has occurred.

A mismatch in the checksum values computed by the host and the

AD4080 interface results in setting the CRC_ERR flag (CRC_ERR

= 1) in the Interface Status A register (see the Interface Status

A Register section, Address 0x11). During a write access, a CRC

error invalidates the most recent register data as well as any sub-

sequent register data writes if in streaming mode (SINGLE_INST

= 0), which prevents loading any potentially corrupted data into

the configuration memory. In response to a CRC event, the host

controller is required to initiate a new SPI frame to retry configura-

tion of the effected memory locations. In the event the CRC_ERR

is detected during a data read, the host controller must discard

the received data and retry the data read in a new SPI frame.

Clear the CRC_ERR flag before any attempt to initiate a repeated

read or write to the configuration memory to allow detection of any

subsequent errors. The error flag is cleared by writing code 0x08 to

the Interface Status A register to set the CRC_ERR bit to a Logic 1.

It is recommended that an immediate read of the Interface Status A

was successful.

The configuration CRC function is disabled by default and can

be enabled through two complementary bit fields, CRC_ENABLE

and CRC_ENABLEB, in the Interface Configuration C register (see

the Interface Configuration C Register section, Address 0x10). To

enable the CRC function, set the CRC_ENABLE bits to 1 and the

CRC_ENABLEB bits to 10. Each of the complementary CRC bit

fields is 2-bit wide, and any combination other than that specified

results in the function remaining disabled. It is important to note

that once the CRC function is enabled, a valid checksum from

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