AD4080BBCZ datasheet(44/94 Pages) AD

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Data Sheet

AD4080

DIGITAL INTERFACE

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Rev. A | 44 of 94

Figure 72. Configuration SPI Timing, Data Read Frame, Continuous SCLK

LVDS DATA INTERFACE

LVDS Data Interface Configuration

The LVDS interface consists of up to five pairs of differential

signals. The data clock input pair (CLK+ and CLK−), echoed data

clock output pair (DCO+ and DCO−), two data output lanes (DA+

and DA− , DB+ and DB− ), and optionally, the conversion clock can

be configured as either an LVDS pair (CNV+ and CNV−) or as a

CMOS using CNV+, where for this case, CNV− is connected to

GND. This user selection is configured using the LVDS_CNV_EN

bit in the ADC Data Interface Configuration B register (see the ADC

Data Interface Configuration B Register section, Address 0x16).

The data lanes use a DDR scheme, and each scheme can support

a throughput of up to 800 (Mbps). By default, LVDS is selected as

the primary data interface for accessing conversion results.

To achieve maximum throughput, it is necessary that while a con-

version is performed the result of the previous conversion is read.

For this reason, it is critical that both the rising and falling edges

of CNV+ and CNV− are closely time aligned to the rising edge of

CLK+ and CLK−. To avoid introducing noise into the conversion

result, the CLK+ and CLK− edge placement must be aligned to

within ±535 ps (tCCA) of the interface clock (CLK±), as specified in

Table 2.

The data interface is highly configurable allowing the customization

of the output stream to meet a wide range of applications. Configu-

ration options include the number of active lanes (1, 2), self clocked

and echo clock modes, interface test functions, and data encoding.

LVDS interface mode is used in applications where continuous

conversion at rates exceeding 1 MHz is required.

Transmission of the result data occurs MSB first and is output after

the amount of time specified in detail in the ADC Result Latency

and LVDS Interface Alignment section.

LVDS Active Data Lane Count

The LVDS interface can be configured to output the result data

on either one or two data lanes, which is controlled by the

SPI_LVDS_LANES bit in the ADC Data Interface Configuration

A register (see the ADC Data Interface Configuration A Register

section, Address 0x15). By default, this bit is set to 0 (one lane

active), and setting SPI_LVDS_LANES = 1 uses two data lanes.

Note that this bit is also used to configure the number of active data

lanes for the SPI.

In single lane operation, Data Lane DA+ and Data Lane DA− is

enabled as the primary data output, and the conversion result is

shifted out serially, MSB first, using 10 interface clocks applied to

CLK+ and CLK− inputs per conversion. The result data is shifted

out of the device on each edge of the echo clock outputs, DCO+

and DCO−. The result MSB (D19) and all odd numbered data bits

are output on the falling edge of the interface clock. Conversely,

the even numbered data bits are output on the rising edge of the

interface clock.

In dual lane configuration, the result data is shifted out in parallel,

2 bits per clock edge, MSBs first. As a result, only five interface

clocks are required per conversion. As the data access period is

equivalent to the conversion period, the interface clock frequency

is reduced by a factor of two relative to the single lane case. As a

consequence of the increased interface clock period, see the ADC

Result Latency and LVDS Interface Alignment section for the timing

and latency implications on both the single lane and dual lane count

configurations.

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