AD4080BBCZ datasheet(49/94 Pages) AD

49 / 94 page

Data Sheet

AD4080

DIGITAL INTERFACE

analog.com

Rev. A | 49 of 94

This feature allows the user to align and test the data interface to

their digital host. When the INTF_CHK_EN bit is unset, the normal

conversion results are output to the LVDS interface immediately.

This method is useful for alignment, particularly for self clock mode

cases where unknown PCB propagation delays may be present

between the AD4080 and its digital host controller. Note that this

feature was specifically designed to help output LVDS data with the

LVDS clock of the digital host by using static data, and the feature

does not indicate if the LVDS_CNV_CLK_CNT setting is used.

Table 21. LVDS_CNV_CLK_CNT Settings for Various Sample Rates (with gain correction applied)

Sample Rate (MSPS)

LVDS Lanes

fCLK (MHz)

tCLK (ns)

(tMSB/tCLK) + 1.5

LVDS_CNV_CLK_CNT Setting

400

2.500

10.46

350

2.857

9.34

300

3.333

8.22

250

4.000

7.1

200

5.000

5.98

150

6.666

4.86

200

5.000

5.98

LVDS Data Transfer Latency

Where the user is concerned in knowing the overall latency from

when an individual ADC conversion is initiated to the time when

the LSB has reached the host controller, it is important to consider

the data transfer latency. The total latency observed is the sum of

the ADC latency and the data transfer latency, in this case, the

LVDS_CNV_CLK_CNT is set to achieve minimum ADC latency.

Additional clock cycles more than the minimum required incur

additional LVDS clock cycles of latency to the overall latency, as is

shown in Figure 80.

The data transfer latency on the LVDS interface depends on the

following parameters:

►

LVDS clock period, tCLK

►

Number of active LVDS lanes, NLANES

►

Number of bits to be read, NBITS

Calculate the latency as follows:

Data Transfer Latency = NBITSNLANES×tCLK

For applications that require extremely low latencies, note that as

the data is transferred MSB to LSB in both single and dual lane

modes, and that there is no requirement to fully read a result from

the interface, the data transfer latency can be reduced for lower

resolution results (that is, NBITS can be chosen to be smaller than

the maximum 20 bits available).

Figure 80. LVDS Data Transfer Latency

AD4080BBCZ Datasheet(PDF) 49 Page - Analog Devices

AD4080BBCZ Datasheet(HTML) 49 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

Datasheet Download

Link URL