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ADC12DS080 Datasheet(PDF) 2 Page - Texas Instruments |
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ADC12DS080 Datasheet(HTML) 2 Page - Texas Instruments |
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2 / 33 page ![]() ADC12DS080 (top view) 1 2 3 4 5 6 7 8 9 10 11 12 14 15 13 VRPA VDR 32 31 45 44 43 42 41 40 39 38 37 35 34 33 36 OUTCLK+ N/C SD0_B- OUTCLK- FRAME- FRAME+ VINA- VINA+ AGND AGND AGND VA AGND VINB- VCMOA VRNA VCMOB VRNB VRPB SD0_B+ SD1_B- SD1_B+ DRGND SD0_A- SD0_A+ SD1_A- SD1_A+ * Exposed Pad VINB+ 12-Bit Pipelined ADC Core Parallel -to- Serial Reference A Reference B DLL & Timing Generation SPI Interface & Control Registers VINA 2 12 2 2 SD0_A SD1_A CHANNEL A 12-Bit Pipelined ADC Core Parallel -to- Serial VINB 2 12 2 2 SD0_B SD1_B CHANNEL B 2 2 FRAME OUTCLK CLK VREF Ref.Outputs Ref.Outputs ORB ORA SCSb SCLK SPI_EN SDI SDO 3 3 ADC12DS080 SNAS443A – MARCH 2008 – REVISED MARCH 2013 www.ti.com Block Diagram Connection Diagram Figure 1. WQFN Package See Package Number NKA0060A 2 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: ADC12DS080 |
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